Device and method for automatically generating an appropriate number of wait cycles while reading a nonvolatile memory
View Patent ↗An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and generates a wait-code enabling signal, and a wait-state generating unit, which is connected to the protocol-decoding unit and outputs wait codes upon receipt of the wait-code enabling signal. When the memory ends reading, as signaled by switching of a read-state signal, a wait-state disabling circuit generates and supplies an end-of-waiting control signal to the wait-state generating unit, which thus outputs an end-of-waiting code.
1. An interface for managing exchange of information between a bus system and a memory during reading, according to a communication protocol, the interface comprising:
input/output terminals configured to be connected to said system bus;
a protocol-decoding unit configured to receive from said input/output terminals commands and information for managing reading and configured to generate a wait-code enabling signal;
a wait-state generating unit connected to said protocol-decoding unit and configured to supply wait codes to said first input/output terminals upon reception of said wait-code enabling signal; and
a wait-state disabling circuit configured to generate an end-of-waiting control signal to be supplied to said wait-state generator upon reception of a read-state signal from said memory, said wait-state generating unit configured to supply an end-of-waiting code to said input/output terminals upon reception of said end-of-waiting control signal.
2. The interface according to claim 1 wherein said wait-state disabling circuit includes:
an end-of-reading sensing stage configured to receive said read-state signal and configured to generate an end-of-waiting request signal upon detection of a pre-set switching edge of said read-state signal; and
an end-of-waiting forcing stage configured to receive said end-of-waiting request signal and a synchronization signal and configured to supply said end-of-waiting control signal in presence of a pre-set state of said end-of-waiting request signal and upon reception of a pre-set switching edge of said synchronization signal.
3. The interface according to any of claims 1 , further comprising a control unit configured to receive an enabling signal and a synchronization signal, said control unit configured to generate, upon reception of said enabling signal and synchronously with said synchronization signal, a first enabling signal and a second enabling signal respectively supplied to said protocol-decoding unit and to said wait-state generating unit.
4. The interface according to any of claim 1 further comprising integration means configured to integrate said interface in a memory device with said memory.
5. The interface according to claim 1 wherein the wait-state generating unit and the wait-state disabling circuit are distinct functional units.
6. The interface according to claim 2 wherein said end-of-reading sensing stage includes:
an end-of-reading detector configured to receive said read-state signal and said wait-code enabling signal and configured to generate an end-of-reading signal in the presence of a pre-set state of said wait-code enabling signal and upon detection of said pre-set switching edge of said read-state signal; and
an end-of-reading memory configured to receive said end-of-reading signal and to generate said end-of-waiting signal.
7. The interface according to claim 3 wherein said control unit is a state machine configured to generate state signals including, in sequence:
said first enabling signal;
a third enabling signal supplied to a switch unit for transmission of address signals from said input/output terminals to said memory;
said second enabling signal; and
a fourth enabling signal for enabling data transmission from said memory to said input/output terminals.
8. The interface according to claim 6 wherein said end-of-reading memory is a latch of an SR type, and said end-of-waiting forcing stage is a master/slave flip-flop.
9. A method for managing exchange of information between a system bus and a memory during a reading step, according to a communication protocol, the method comprising:
receiving commands and information for management of the reading step;
decoding said commands;
generating a wait-code enabling signal upon reception of a reading code;
generating wait codes upon reception of said wait-code enabling signal;
receiving a read-state signal;
generating an end-of-waiting control signal as a result of reception of a pre-set switching edge of said read-state signal; and
generating an end-of-waiting code upon reception of said end-of-waiting control signal.
10. The method according to claim 9 wherein said generating an end-of-waiting control signal includes:
generating an end-of-waiting request signal upon detection of said pre-set switching edge of said read-state signal;
receiving a synchronization signal; and
generating said end-of-waiting control signal in presence of a pre-set state of said end-of-waiting request signal and upon reception of a pre-set switching edge of said synchronization signal.
11. A system for managing exchange of information between a system bus and a memory, the system comprising:
means for receiving commands and information for management of the reading step;
means for decoding said commands;
means for generating a wait-code enabling signal upon reception of a reading code;
means for generating wait codes upon reception of said wait-code enabling signal;
means for receiving a read-state signal;
means for generating an end-of-waiting control signal after reception of a pre-set switching edge of said read-state signal; and
means for generating an end-of-waiting code upon reception of said end-of-waiting control signal.
12. The system according to claim 11 wherein said means for generating an end-of-waiting control signal includes:
means for generating an end-of-waiting request signal upon detection of said pre-set switching edge of said read-state signal;
means for receiving a synchronization signal; and
means for generating said end-of-waiting control signal in presence of a pre-set state of said end-of-waiting request signal and upon reception of a pre-set switching edge of said synchronization signal.
13. For operation with a system bus, a memory device comprising:
a memory;
an interface configured to manage exchange of information between the system bus and the memory during reading, according to a communication protocol, the interface including:
input/output terminals configured to be connected to said system bus;
a protocol-decoding unit configured to receive from said input/output terminals commands and information for managing reading and configured to generate a wait-code enabling signal;
a wait-state generating unit connected to said protocol-decoding unit and configured to supply wait codes to said first input/output terminals upon reception of said wait-code enabling signal; and
a wait-state disabling circuit configured to generate an end-of-waiting control signal to be supplied to said wait-state generator upon reception of a read-state signal from said memory, said wait-state generating unit configured to supply an end-of-waiting code to said input/output terminals upon reception of said end-of-waiting control signal.
14. The interface according to claim 13 wherein said wait-state disabling circuit includes:
an end-of-reading sensing stage configured to receive said read-state signal and configured to generate an end-of-waiting request signal upon detection of a pre-set switching edge of said read-state signal; and
an end-of-waiting forcing stage configured to receive said end-of-waiting request signal and a synchronization signal and configured to supply said end-of-waiting control signal in presence of a pre-set state of said end-of-waiting request signal and upon reception of a pre-set switching edge of said synchronization signal.
15. The interface according to claim 13 , further comprising a control unit configured to receive an enabling signal and a synchronization signal, said control unit configured to generate, upon reception of said enabling signal and synchronously with said synchronization signal, a first enabling signal and a second enabling signal respectively supplied to said protocol-decoding unit and to said wait-state generating unit.
16. The interface according to claim 13 further comprising integration means configured to integrate said interface in a memory device with said memory.
17. The interface according to claim 14 wherein said end-of-reading sensing stage includes:
an end-of-reading detector configured to receive said read-state signal and said wait-code enabling signal and configured to generate an end-of-reading signal in the presence of a pre-set state of said wait-code enabling signal and upon detection of said pre-set switching edge of said read-state signal; and
an end-of-reading memory configured to receive said end-of-reading signal and to generate said end-of-waiting signal.
18. The interface according to claim 17 wherein said end-of-reading memory is a latch of an SR type, and said end-of-waiting forcing stage is a master/slave flip-flop.
19. The interface according to claim 15 wherein said control unit is a state machine configured to generate state signals including, in sequence:
said first enabling signal;
a third enabling signal supplied to a switch unit for transmission of address signals from said input/output terminals to said memory;
said second enabling signal; and
a fourth enabling signal for enabling data transmission from said memory to said input/output terminals.
20. A computer system comprising:
a system bus;
a processor communicatively linked to the system bus;
a memory;
an interface communicatively linked to the system bus and to the memory, the interface configured to manage exchange of information between the system bus and the memory during reading, according to a communication protocol, the interface including:
input/output terminals configured to be connected to said system bus;
a protocol-decoding unit configured to receive from said input/output terminals commands and information for managing reading and configured to generate a wait-code enabling signal;
a wait-state generating unit connected to said protocol-decoding unit and configured to supply wait codes to said first input/output terminals upon reception of said wait-code enabling signal; and
a wait-state disabling circuit configured to generate an end-of-waiting control signal to be supplied to said wait-state generator upon reception of a read-state signal from said memory, said wait-state generating unit configured to supply an end-of-waiting code to said input/output terminals upon reception of said end-of-waiting control signal.
21. The interface according to claim 20 wherein said wait-state disabling circuit includes:
an end-of-reading sensing stage configured to receive said read-state signal and configured to generate an end-of-waiting request signal upon detection of a pre-set switching edge of said read-state signal; and
an end-of-waiting forcing stage configured to receive said end-of-waiting request signal and a synchronization signal and configured to supply said end-of-waiting control signal in presence of a pre-set state of said end-of-waiting request signal and upon reception of a pre-set switching edge of said synchronization signal.
22. The interface according to any of claims 20 , further comprising a control unit configured to receive an enabling signal and a synchronization signal, said control unit configured to generate, upon reception of said enabling signal and synchronously with said synchronization signal, a first enabling signal and a second enabling signal respectively supplied to said protocol-decoding unit and to said wait-state generating unit.
23. The interface according to claim 20 further comprising integration means configured to integrate said interface in a memory device with said memory.
24. The interface according to claim 21 wherein said end-of-reading sensing stage includes:
an end-of-reading detector configured to receive said read-state signal and said wait-code enabling signal and configured to generate an end-of-reading signal in the presence of a pre-set state of said wait-code enabling signal and upon detection of said pre-set switching edge of said read-state signal; and
an end-of-reading memory configured to receive said end-of-reading signal and to generate said end-of-waiting control signal.
25. The interface according to claim 24 wherein said end-of-reading memory is a latch of an SR type, and said end-of-waiting forcing stage is a master/slave flip-flop.
26. The interface according to claim 22 wherein said control unit is a state machine configured to generate state signals including, in sequence:
said first enabling signal;
a third enabling signal supplied to a switch unit for transmission of address signals from said input/output terminals to said memory;
said second enabling signal; and
a fourth enabling signal for enabling data transmission from said memory to said input/output terminals.
27. An interface for managing exchange of information between a bus system and a memory during reading, according to a communication protocol, the interface comprising:
input/output terminals configured to be connected to said system bus;
a protocol-decoding module configured to receive from said input/output terminals commands and information for managing reading and configured to generate a wait-code enabling signal;
a wait-state generating module connected to said protocol-decoding module and configured to supply wait codes to said first input/output terminals upon reception of said wait-code enabling signal; and
a wait-state disabling module configured to generate an end-of-waiting control signal to be supplied to said wait-state generator upon reception of a read-state signal from said memory, said wait-state generating module configured to supply an end-of-waiting code to said input/output terminals upon reception of said end-of-waiting control signal.
28. The interface according to claim 27 wherein said wait-state disabling module includes:
an end-of-reading sensing stage configured to receive said read-state signal and configured to generate an end-of-waiting request signal upon detection of a pre-set switching edge of said read-state signal; and
an end-of-waiting forcing stage configured to receive said end-of-waiting request signal and a synchronization signal and configured to supply said end-of-waiting control signal in presence of a pre-set state of said end-of-waiting request signal and upon reception of a pre-set switching edge of said synchronization signal.
29. The interface according to claims 27 , further comprising a control module configured to receive an enabling signal and a synchronization signal, said control module configured to generate, upon reception of said enabling signal and synchronously with said synchronization signal, a first enabling signal and a second enabling signal respectively supplied to said protocol-decoding module and to said wait-state generating module.
30. The interface according to claim 27 further comprising integration means configured to integrate said interface in a memory device with said memory.
31. The interface according to claim 28 wherein said end-of-reading sensing stage includes:
an end-of-reading detector configured to receive said read-state signal and said wait-code enabling signal and configured to generate an end-of-reading signal in the presence of a pre-set state of said wait-code enabling signal and upon detection of said pre-set switching edge of said read-state signal; and
an end-of-reading memory configured to receive said end-of-reading signal and to generate said end-of-waiting control signal.
32. The interface according to claim 29 wherein said control module is a state machine configured to generate state signals including, in sequence:
said first enabling signal;
a third enabling signal supplied to a switch module for transmission of address signals from said input/output terminals to said memory;
said second enabling signal; and
a fourth enabling signal for enabling data transmission from said memory to said input/output terminals.
33. The interface according to claim 31 wherein said end-of-reading memory is a latch of an SR type, and said end-of-waiting forcing stage is a master/slave flip-flop.