Line selector for a matrix of memory elements
View Patent ↗A line selector for a matrix of memory elements, for example a word line selector, comprises a plurality of line group selection circuits, each one allowing the selection of a respective group of matrix lines according to an address; each matrix line group includes at least one matrix line. Flag means are associated with each line group, that can be set to declare a pending status of a prescribed operation, for example an erase operation, for the respective matrix line group. Means are provided for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation, in alternative to the respective line group selection circuit. The flag means enable, when set, the execution of the prescribed operation on the respective matrix line group.
1. A line selector for a matrix of memory elements, comprising
a plurality of matrix line group selection circuits, each one allowing the selection of a respective group of matrix lines according to a first address, each matrix line group including a plurality of matrix lines,
associated with each matrix line group selection circuit, a respective plurality of matrix line selection circuits, each one for allowing the selection of at least one respective matrix line within the respective matrix line group according to a second address, the matrix line selection circuits comprising matrix line driver circuits for driving potentials of the matrix lines,
flag means associated with each matrix line group, that can be set to declare a pending status of a prescribed operation to be conducted globally on the memory elements of the respective matrix line group, the flag means enabling, when set, the execution of the prescribed operation on the respective matrix line group, and
means for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation, in alternative to the respective line group selection circuit.
2. The line selector according to claim 1 , in which the matrix lines are word lines.
3. The line selector according to claim 2 , in which the prescribed operation is an erase operation of the memory elements.
4. The line selector according to claim 3 , in which the flag means are reset after the respective word line group has been erased.
5. The line selector according to claim 4 , in which the flag means are reset after the respective word line group has passed an erase verify operation.
6. The line selector according to claim 5 , further comprising setting means and reselling means, associated with each flag means for selling and, respectively, reselling the associated flag means, the setting means and resetting means being enabled by the respective line group selection circuit according to the first address.
7. The word line selector according to claim 2 , in which the flag means comprises a set-reset flip-flop.
8. The line selector according to claim 2 , in which the means for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation comprise means for disconnecting the line group selection circuit from a respective line group selection signal line, and means for transferring onto the line group selection signal line a state corresponding to that of the respective flag means.
9. The line selector according to claim 2 , in which a word line driver reset circuit is associated with each line group selection circuit, activatable for resetting the word line driver circuits of the associated word line selection circuit.
10. The line selector according to claim 9 , in which the word line driver reset circuit, when activated, resets the word line driver circuits of the associated word line selection circuit only if the respective group of word lines is selected.
11. A method of conducting a prescribed operation on a matrix of memory elements, comprising:
providing a matrix line selector having a plurality of matrix line group selection circuits, each matrix line group selection circuit allowing the selection of a respective group of matrix lines according to a first address, each matrix line group including a plurality of matrix lines,
providing a plurality of matrix line selection circuits associated with each matrix line group selection circuit, each matrix line selection circuit allowing the selection of at least one respective matrix line within the respective matrix line group according to a second address, the matrix line selection circuits comprising matrix line driver circuits for driving potentials of the matrix lines,
associating with each matrix line group a respective flag,
selectively selling at least one of the flags, to declare a pending status of the prescribed operation to be conducted globally on memory elements of the respective matrix line group, the at least one set flag enabling the execution of the prescribed operation globally on memory elements of the respective matrix line group, and
entrusting the flags with the selection of the respective matrix line group, as an alternative to the respective line group selection circuit.
12. The method according to claim 11 , in which the matrix lines are word lines.
13. The method according to claim 12 , in which the prescribed operation is an erase operation.
14. The method according to claim 13 , in which the setting of the at least one flag comprises selecting the matrix group via the respective line group selection circuit.
15. The method according to claim 14 , further comprising applying at least one erase pulse.
16. The method according to claim 15 , further comprising verifying an outcome of the at least one erase pulse by accessing the word lines in the word line group associated with the at least one set flag.
17. The method according to claim 16 , in which the verifying further comprises resetting the at least one set flag if the outcome of the at least one erase pulse is positive.
18. The method according to claim 17 , in which the resetting the at least one set flag further comprises selecting the associated word line group via the respective line group selection circuit.
19. The method according to claim 18 , further comprising applying additional erase pulses and verifying the outcome of each additional erase pulse, until the at least one set flag is reset.
20. A memory comprising a matrix of memory elements and a line selector for selecting lines of the matrix, wherein the line selector is realized according to claim 1 .
21. A memory, comprising:
rows of memory cells each coupled to a respective word line, the rows arranged in groups of multiple rows;
status circuits each associated with a respective one of the groups of memory rows and each operable to store a flag that allows a predetermined operation to be performed to the memory cells within the respective group;
a selection circuit coupled to the status circuits and operable to load the flag into selected ones of the status circuits without writing data to the memory cells within the memory-row groups respectively associated with the selected status circuits; and
a control circuit coupled to the groups of memory rows and operable to perform the predetermined operation on only memory cells within the groups of memory rows respectively associated with status circuits that are storing the flag.
22. The memory of claim 21 wherein the selection circuit further comprises:
a row address selection circuit operable to select a row of memory cells based upon a first address signal; and
a column address selection circuit operable to select a column of memory cells based upon a second address signal.
23. The memory of claim 21 , further comprising a resetting circuit operable to reset the status circuits to a finished state after the operation performed on the memory cells within the associated groups of memory rows has been verified.
24. An electronic system, comprising:
a memory, including,
rows of memory cells arranged in groups each including multiple rows,
status circuits each associated with a respective one of the groups of rows and each operable to store a flag that allows a predetermined operation to be performed to the memory cells within the respective group,
a selection circuit coupled to the status circuits and operable to load the flag into selected ones of the status circuits without writing data to the memory cells within the groups of memory rows respectively associated with the selected status circuits, and
a control circuit coupled to the groups of memory rows and operable to perform the predetermined operation on only memory cells within the groups of memory rows respectively associated with status circuits that are storing the flag.
25. The electronic system of claim 24 wherein the memory comprises an electronic erasable and programmable memory.
26. A method, comprising:
loading a first flag into a storage circuit associated with a group of memory rows without writing data to memory cells within the group; and performing a first predetermined operation on only memory cells within groups of memory rows associated with respective storage circuits that are storing the flag.
27. The method of claim 26 , further comprising:
loading a second flag into the storage circuit after performing the first predetermined operation on the memory cells within the associated group of memory rows; and
performing a second predetermined operation on only the memory cells within the groups of memory rows associated with respective storage circuits that are storing the second flag.
28. The method of claim 26 wherein the first predetermined operation comprises an erase operation.
29. The method of claim 26 wherein the second predetermined operation comprises an erase-verify operation.