Distribution of an electric quantity through a circuit
View Patent ↗A method of distributing an electric quantity through an electronic circuit for local exploitation by at least one circuit block of the electronic circuit that includes providing in the electronic circuit first and second conductive lines, the first conductive line distributing a first electric potential and the second conductive line carrying a second electric potential that is a dedicated reference electric potential for the first electric potential, the first and second electric potentials corresponding to the distributed electric quantity, and locally exploiting the distributed electric quantity by at least one circuit block of the electronic circuit, by locally reconstructing the distributed electric quantity from the first and second electric potentials without perturbing them, particularly without either sinking or injecting any significant current from or into the first and second conductive lines.
1. A method of distributing a reference voltage signal through an integrated circuit (IC) including a plurality of circuit blocks, comprising:
generating the reference voltage signal; and
distributing, to the plurality of circuit blocks, the reference voltage signal with a reference voltage line at a reference voltage potential relative to a reference ground line, wherein the reference ground line is coupled to a common ground line at a first node and is further coupled to a gate of a first P-channel transistor in each of the plurality of circuit blocks, the first P-channel transistor having a drain coupled to the common ground line at a second node, wherein the reference voltage line is coupled to a first N-channel transistor gate of each of the plurality of circuit blocks, the first N-channel transistor having a source coupled in series to a source of the first P-channel transistor to form an input interface for each of the plurality of circuit blocks.
2. The method as in claim 1 , further comprising operating both the first P-channel and first N-channel transistors of each input interface in saturation.
3. The method as in claim 1 , wherein generating the reference voltage signal further comprises injecting a reference current into a second N-channel transistor and a second P-channel transistor, each in a diode configuration and connected with sources in series, and with the second P-channel transistor having a drain coupled to the common ground; and
wherein distributing the reference voltage signal further comprises setting the reference voltage line potential to the voltage of the second N-channel gate electrode and setting the reference ground line potential to the voltage of the second P-channel gate electrode.
4. The method as in claim 1 , further comprising:
reconstructing the reference voltage signal distributed to each circuit block by coupling a remaining circuitry within each circuit block to the drain of the first N-channel transistor.
5. The method as in claim 1 , further comprising:
operating the first N-channel and first P-channel transistors with source electrode degeneration.
6. The method as in claim 5 , further comprising:
coupling a degenerated resistor between the first N-channel transistor and the first P-channel transistor.
7. The method as in claim 3 , wherein the reference voltage line is dedicated to the first and second N-channel gate electrode connections and wherein the ground reference line is dedicated to the first and second P-channel gate electrode connections.
8. An integrated circuit (IC) comprising:
a reference voltage signal generator;
a plurality of circuit blocks, each of the plurality of circuit blocks including a first P-channel transistor having a drain coupled to a common ground line at a first node;
a reference voltage line coupled to each of the plurality of circuit blocks; and a reference ground line coupled to the common ground line at a second node and further coupled to a gate of the first P-channel transistor in each of the plurality of circuit blocks, wherein the reference voltage line is coupled to a gate of a first N-channel transistor in each of the plurality of circuit blocks, the first N-channel transistor having a source coupled in series to a source of the first P-channel transistor in each circuit block to form an input interface for each of the plurality of circuit blocks.
9. The IC as in claim 8 , wherein reference voltage signal generator further comprises:
a second N-channel transistor and a second P-channel transistor, each transistor in a diode configuration and with sources connected in series, with the second N-channel transistor coupled to a current source and the second P-channel transistor drain coupled to the common ground;
a gate electrode of the second N-channel transistor further coupled to the reference voltage line; and
a gate electrode of the second P-channel transistor further coupled to the reference ground line.
10. The IC as in claim 8 , further comprising:
a remaining circuitry in each of the circuit blocks, the remaining circuitry coupled to the drain of the first N-channel transistor.
11. The IC as in claim 8 , further comprising:
a degenerated resistor between the first N-channel transistor and the first P-channel transistor.
12. The IC as in claim 9 , wherein the reference voltage line is dedicated to the first and second N-channel gate electrode connections and wherein the ground reference line is dedicated to the first and second P-channel gate electrode connections.
13. The IC as in claim 9 , wherein the IC is a non-volatile memory circuit and each circuit block includes a memory cell.
14. A non-volatile memory circuit comprising:
a reference voltage signal generator;
a plurality of memory cells, each of the plurality of memory cells coupled to a reference voltage input interface including a first P-channel transistor having a drain coupled to a common ground line at a first node;
a reference voltage line coupled to each of the plurality of reference voltage input interfaces; and
a reference ground line coupled to the common ground line at a second node and further coupled to a gate of the first P-channel transistor of each of the reference voltage input interfaces, wherein the reference voltage line is coupled to a first N-channel transistor gate of each of the reference voltage input interfaces, the first N-channel transistor being coupled in series to the first P-channel transistor.
15. The non-volatile memory circuit as in claim 14 , wherein reference voltage signal generator further comprises:
a second N-channel transistor and a second P-channel transistor, each transistor a diode configuration and with sources connected in series, with the second N-channel transistor coupled to a current source and the second P-channel transistor drain coupled to the common ground;
a gate electrode of the second N-channel transistor further coupled to the reference voltage line; and
a gate electrode of the second P-channel transistor further coupled to the reference ground line.
16. The non-volatile memory circuit as in claim 14 , further comprising:
a flash memory device in each of the memory cells, the flash memory device coupled to the drain of the first N-channel transistor.
17. The IC as in claim 14 , further comprising:
a degenerated resistor between the first N-channel transistor and the first P-channel transistor of each reference voltage input interface.