Semiconductor memory device with a page buffer having an improved layout arrangement
View Patent ↗A memory device is provided. The memory device includes a matrix of memory cells adapted to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction; a page buffer adapted to interface the matrix with a downstream circuitry, the page buffer comprising a plurality of read/program units. Each read/program unit is associated with at least one bit line. The memory device further includes at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction. Each group comprises at least one signal track shared by the at least two read/program units of the group.
1. A memory device, including:
a matrix of memory cells structured to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction;
a page buffer structured to interface the matrix with a downstream circuitry, the page buffer comprising a plurality of read/program units, each read/program unit being associated with and operatively couplable to at least one bit line;
at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction, said at least two groups being generically aligned along a second direction transversal to the first direction;
a plurality of signal tracks respectively associated with said groups, for conveying signals corresponding to data read from the memory cells to the downstream circuitry, each signal track being shared by the at least two read/program units of the associated group; and
means for selectively assigning each signal track to one of the associated read/program units at a time among the at least two read/program units of the group associated with said signal track.
2. The memory device of claim 1 , wherein said signal track crosses the read/program units of the respective group, extending along the first direction.
3. The memory device of claim 1 , wherein each one of said read/program units is associated with a respective one of the bit lines and comprises a coupling signal line electrically couplable to the bit line associated with the read/program unit, for applying to the coupled bit line one among two electric potential values, the coupling signal line extending across all the read/program units of the corresponding group.
4. The memory device of claim 3 , wherein each of said at least two groups of at least two read/program units includes N read/program units with N coupling signal lines, and the N coupling signal lines extend generally along the first direction while being intertwined with each other.
5. The memory device of claim 4 , wherein:
each group of N read/program units has associated therewith N positions defined along the second direction;
each coupling signal line of the N coupling signal lines of the group includes N line segments, the N line segments occupying each a different one of the N positions.
6. The memory device of claim 5 , wherein said segments have substantially equal lengths.
7. The memory device of claim 6 , wherein each segment has a length substantially equal to a length of the generic read/program unit along the first direction.
8. The memory device according to claim 3 , wherein said signal track of one of the groups is arranged between the coupling signal lines associated with the at least two read/program units of the group.
9. A memory device comprising:
an array of memory cells having a plurality of bit lines;
a plurality of read/program units arranged in a plurality of columns, each column forming a group of the units and extending in a first direction, each unit being coupled to one or more bit lines and having a signal line configured to supply a voltage to the one or more bit lines of the unit; and
a plurality of output tracks associated respectively with the groups, the output tracks being configured to output data to circuitry downstream, wherein, for each group, the units in the group share and are coupled to the output track associated with the group; and the output track associated with the group crosses the read/program units of the group, extending along the first direction.
10. The memory device according to claim 9 wherein, for each group, the signal lines of the units of the group extend across a length of the group of units in intertwining paths.
11. The memory device according to claim 10 wherein, for each group, the signal lines of the group are formed in a plurality of layers on a substrate.
12. The memory device according to claim 9 wherein, for each group, the output track of the group extends centrally of the group of units in the first direction.
13. A memory device comprising:
an array of memory cells having a plurality of bit lines;
a plurality of read/program units arranged in a plurality of columns, each column forming a group of the units and extending in a first direction, each unit being coupled to one or more bit lines and having a signal line configured to supply a voltage to the one or more bit lines of the unit, wherein:
the units in a group share and are coupled to an output track configured to output data to circuitry downstream; and
the signal lines of the units in a group have an approximately same length.
14. The memory device according to claim 13 wherein, for each group, the signal lines of the units of the group extend across a length of the group of units in intertwining paths.
15. The memory device according to claim 14 wherein, for each group, the signal lines of the group are formed in a plurality of layers on a substrate.
16. The memory device according to claim 13 wherein, for each group, the output track of the group extends centrally of the group of units in the first direction.
17. A method for implementing a page buffer in a memory device, the page buffer having a plurality of read/program units, the memory device having memory cells connected to array bit lines, the method comprising:
organizing the units into a plurality of columns, each column forming a group of units, each unit being coupled to one or more bit lines and having a signal line configured to apply a voltage to a bit line coupled to the unit;
coupling each unit in a group to a same signal track configured to output data to circuitry downstream; and
forming the signal line of each unit in a group to be approximately the same length.
18. The method according to claim 17 comprising:
intertwining the signal lines of a group across the length of the column of units.