IP Library Granted Patent US 7,216,212
Granted Patent B2
US 7,216,212 · App. 10/387,141 · Granted May 8, 2007

Semiconductor memory with self-refresh capability

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Quick Facts
Patent No.
US 7,216,212
App. No.
10/387,141
Granted
May 8, 2007
Kind
B2
Abstract

A memory device comprises a plurality of banks of storage locations accessible in response to access requests. Data refresh means are provided for refreshing data stored in the storage locations within prescribed times, whereby the memory device autonomously perform a refresh. A cache memory is embedded in the memory device. The cache memory has a plurality of cache storage locations for storing data contained in recently accessed storage locations. Access control means control the access to the storage locations and to the cache storage locations in response to the access requests: an access request is diverted to the cache memory whenever access to anyone of the recently accessed storage locations is requested. Any cache storage location is freely associable to any storage location in any bank, the association between any cache storage location and a storage location in the plurality of banks being established by a storage location association table in the access control means.

Claims (36)

1. A memory, comprising:

semiconductor material;

memory banks disposed in the semiconductor material and each having a number of memory locations;

a cache disposed in the semiconductor material, coupled to the memory banks, and having storage locations that are each mappable to any one of the memory locations; and

an address table disposed in the semiconductor material, coupled to the cache, and operable to map a storage location to a memory location and to indicate a time elapsed since an access of the memory location.

2. A memory, comprising:

memory banks each having a number of memory locations;

a cache coupled to the memory banks and having storage locations that are each mappable to any one of the memory locations;

an address table coupled to the cache and operable to map a storage location to a memory location and to indicate a time elapsed since an access of the memory location; and

wherein the address table comprises a DRAM cell operable to store a state that indicates the time elapsed since the access of the memory location.

3. A system, comprising:

a memory having,

a semiconductor material;

memory banks disposed in the semiconductor material and each having a number of memory locations,

a cache disposed in the semiconductor material, coupled to the memory banks, and having storage locations that are each mappable to any one of the memory locations, and

an address table disposed in the semiconductor material, coupled to the cache, and operable to map a storage location to a memory location and to indicate a time elapsed since an access of the memory location.

4. A memory device comprising:

a plurality of banks of storage locations accessible in response to access requests;

data refresh means for refreshing data stored in the storage locations within prescribed times;

a cache memory having a plurality of cache storage locations, for storing data contained in recently accessed storage locations;

access control means for controlling the access to the storage locations and to the cache storage locations in response to the access requests, the access control means diverting an access request to the cache memory whenever access to anyone of the recently accessed storage locations is requested;

wherein any cache storage location is freely associable to any storage location in any bank, the association between any cache storage location and a storage location in the plurality of banks being established by a storage location association table in the access control means;

wherein the storage location association table stores addresses identifying the recently accessed storage locations, and, each time an access request is detected, compares an access request address identifying a storage location to which access is requested with the stored addresses of the recently accessed storage locations; and

wherein the storage location association table stores, for each one of the recently accessed storage locations, an indication of time lapsed from the last access request to the storage location.

5. The memory device according to claim 4 , in which when an access request to a storage location different from the recently accessed storage locations is received, the access control means perform a cache memory allocation procedure, the cache memory allocation procedure comprising copying the data contained in the accessed storage location into the cache memory and storing the address identifying the accessed storage location in the storage location association table.

6. The memory device according to claim 5 , in which the cache memory allocation procedure comprises:

if non-allocated cache storage locations exist, allocating one of the non-allocated cache storage locations, otherwise allocating a cache storage location associated to a storage location for which the indication of time lapsed from the last access request indicates a time lapse greater than a prescribed time.

7. The memory device according to claim 6 , in which when the access detected by the control means is a write access request to a storage location for writing data, the data content of the cache storage location associated with the accessed storage location is modified according to the write data, instead of the data content of the accessed storage location.

8. The memory device according to claim 7 , in which the storage location association table stores, for each one of the recently accessed storage locations, a data modified indication indicative of the fact that the data content of the associated cache storage location has changed due to one or more write access requests to the recently accessed storage location.

9. The memory device according to claim 8 , in which the allocation procedure comprises:

when allocating a cache storage location already associated with a storage location, controlling the data modified indication in the storage location association table to check whether the data content of the cache storage location has been modified and, in the affirmative case, writing back the data content of the cache storage location into the associated storage location before allocating the cache storage location.

10. A method, comprising:

writing data to a first storage location of a physical cache, the first storage location mapped to a first memory location of a physical memory bank;

determining whether at least a predetermined time has elapsed from the writing of the data; and

remapping the first cache storage location to a second memory location of the memory bank if at least the predetermined time has elapsed from the writing of the data.

11. The method of claim 10 , further comprising mapping a second cache storage location to the second memory location if the predetermined time has not elapsed from the writing of the first data.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2013
From: STMICROELECTRONICS, S.R.L. (FORMERLY KNOWN AS SGS-THMSON MICROELECTRONICS S.R.L.)
To: MICRON TECHNOLOGY, INC.
Reel/Frame 031796/0348 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2003
From: BATTAGLIA, FRANCESCO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 014270/0546 →