IP Library Granted Patent US 7,176,748
Granted Patent B2
US 7,176,748 · App. 10/982,528 · Granted Feb 13, 2007

Charge pump circuit with a brief settling time and high output voltage regulation precision

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Quick Facts
Patent No.
US 7,176,748
App. No.
10/982,528
Granted
Feb 13, 2007
Kind
B2
Abstract

A circuit for converting a direct current input voltage into an output voltage greater than the input voltage. The circuit includes a charge pump and a block for generating pulse signals of a predetermined frequency to be applied to a control input of the charge pump. The settling time, i.e. the time necessary for the output voltage to attain its operating value and to maintain it with a given precision, is reduced by providing the circuit with charge injection control via modulation of the duty cycle of the pulse signals as a function of the difference between the output voltage, or a predetermined fraction thereof, and a predetermined reference voltage and in such a manner as to reduce the settling time as the difference diminishes. The circuit includes a regulator that controls the charge pump based upon the predetermined reference voltage.

Claims (55)

1. A circuit for converting an input voltage into an output voltage greater than the input voltage comprising:

a charge pump including a control input;

a pulse signal generator for generating pulse signals of a frequency to be applied to the control input of the charge pump; and

a regulator for regulating the duty cycle of the pulse signals based upon a difference between at least a part of the output voltage and a reference voltage so that the duty cycle is reduced as the difference decreases.

2. A circuit according to claim 1 , wherein the duty cycle is regulated in a discrete manner.

3. A circuit according to claim 1 , wherein the duty cycle is regulated in a continuous manner.

4. A circuit according to claim 1 , wherein the regulator comprises:

at least one comparator having a first input receiving the output voltage, a second input receiving a intermediate reference voltage less than the reference voltage, and an output; and

a pulse width modulator having a first input receiving a clock signal, a control input connected to the output of the at least one comparator, and an output connected to the control input of the charge pump.

5. A circuit according to claim 1 , wherein the regulator comprises:

at least one comparator having a first input receiving the output voltage, a second input receiving a intermediate reference voltage less than the reference voltage, and an output; and

a plurality of pulse width modulators, each of which has a first input receiving a clock signal, a second input, and an output connected to the control input of the charge pump, to modify the duty cycle of the clock signal in a manner different from the other pulse width modulators of the plurality of pulse width modulators; and

a selection logic unit having an input connected to the output of the at least one comparator, and a plurality of selection outputs, each of which is connected to a second input of one of the plurality of pulse width modulators for selective activation of the modulators.

6. A circuit according to claim 1 , wherein the regulator comprises:

a control logic unit having a first input receiving the output voltage, a second input receiving the reference voltage, and an output;

a plurality of pulse width modulators, each of which has a first input receiving a clock signet, a second input, and an output connected to the control input of the charge pump, to modify the duty cycle of the clock signal in a manner different from the other pulse width modulators of the plurality of pulse width modulators; and

a selection logic unit having an input connected to the output of the control logic unit, and a plurality of selection outputs, each of which is connected to a second input of one of the plurality of pulse width modulators for selective activation of the modulators.

7. A circuit according to claim 1 , wherein the regulator comprises a control and pulse width modulating unit having a first modulation input receiving the output voltage, a second input receiving the reference voltage, a third input receiving a clock signal, and an output connected to the control input of the charge pump, the control and pulse width modulating unit also defining the pulse signal generator.

8. A circuit according to claim 1 , further comprising a feedback regulator receiving the output voltage and for controlling the charge pump based upon the output voltage and the reference voltage.

9. A circuit according to claim 4 , further comprising a feedback regulator receiving the output voltage and for controlling the charge pump based upon the output voltage and the reference voltage; wherein the pulse signal generator comprises a transducer circuit connected between the output of the pulse width modulator and the control input of the charge pump and having an enabling/disabling input connected to the feedback regulator.

10. A circuit according to claim 5 , further comprising a feedback regulator receiving the output voltage and for controlling the charge pump based upon the output voltage and the reference voltage; wherein the pulse signal generator comprises an enabling/disabling unit that defines part of the selection logic unit and is connected to the feedback regulator.

11. A circuit according to claim 6 , further comprising a feedback regulator receiving the output voltage and for controlling the charge pump based upon the output voltage and the reference voltage; wherein the pulse signal generator comprises an enabling/disabling unit that defines part of the selection logic unit and is connected to the feedback regulator.

12. A circuit according to claim 10 wherein the feedback regulator comprises a comparator having a first input receiving the output voltage, a second input receiving the reference voltage and an output connected to the selection logic unit.

13. A circuit according to claim 7 , wherein the control and modulation logic unit further comprises a feedback regulator receiving the output voltage and for controlling the charge pump based upon the output voltage and the reference voltage.

14. A device comprising:

a multilevel non-volatile memory; and

a circuit, associated with the memory, for converting an input voltage into an output voltage greater than the input voltage comprising

a charge pump including a control input,

a pulse signal generator for generating pulse signals of a frequency to be applied to the control input of the charge pump, and

a regulator for regulating the duty cycle of the pulse signals based upon a difference between at least a part of the output voltage and a reference voltage so that the duty cycle is reduced as the difference decreases.

15. A device according to claim 14 , wherein the duty cycle is regulated in a discrete manner.

16. A device according to claim 14 , wherein the duty cycle is regulated in a continuous manner.

17. A method for converting an input voltage into an output voltage greater than the input voltage comprising:

providing a charge pump including a control input;

generating pulse signals of a frequency with a pulse signal generator to be applied to the control input of the charge pump; and

regulating the duty cycle of the pulse signals based upon a difference between at least a part of the output voltage and a reference voltage so that the duty cycle is reduced as the difference decreases.

18. A method according to claim 17 , wherein the duty cycle is regulated in a discrete manner.

19. A method according to claim 17 , wherein the duty cycle is regulated in a continuous manner.

20. A method according to claim 17 , wherein regulating the duty cycle comprises providing a regulator including:

at least one comparator having a first input receiving the output voltage, a second input receiving a intermediate reference voltage less than the reference voltage, and an output; and

a pulse width modulator having a first input receiving a clock signal, a control input connected to the output of the at least one comparator, and an output connected to the control input of the charge pump.

21. A method according to claim 17 , wherein regulating the duty cycle comprises providing a regulator including:

at least one comparator having a first input receiving the output voltage, a second input receiving a intermediate reference voltage less than the reference voltage, and an output; and

a plurality of pulse width modulators, each of which has a first input receiving a clock signal, a second input, and an output connected to the control input of the charge pump, to modify the duty cycle of the clock signal in a manner different from the other pulse width modulators of the plurality of pulse width modulators; and

a selection logic unit having an input connected to the output of the at least one comparator, and a plurality of selection outputs, each of which is connected to a second input of one of the plurality of pulse width modulators for selective activation of the modulators.

22. A method according to claim 17 , wherein regulating the duty cycle comprises providing a regulator including:

a control logic unit having a first input receiving the output voltage, a second input receiving the reference voltage, and an output;

a plurality of pulse width modulators, each of which has a first input receiving a clock signal, a second input, and an output connected to the control input of the charge pump, to modify the duty cycle of the clock signal in a manner different from the other pulse width modulators of the plurality of pulse width modulators; and

a selection logic unit having art input connected to the output of the control logic unit, and a plurality of selection outputs, each of which is connected to a second input of one of the plurality of pulse width modulators for selective activation of the modulators.

23. A method according to claim 17 , wherein regulating the duty cycle comprises providing a regulator including a control and pulse width modulating unit having a first modulation input receiving the output voltage, a second input receiving the reference voltage, a third input receiving a clock signal, and an output connected to the control input of the charge pump, the control and pulse width modulating unit also defining the pulse signal generator.

24. A method according to claim 17 , further comprising controlling the charge pump based upon the output voltage and the reference voltage with a feedback regulator receiving the output voltage.

25. A method according to claim 20 , further comprising controlling the charge pump based upon the output voltage and the reference voltage with a feedback regulator receiving the output voltage; wherein the pulse signal generator comprises a transducer circuit connected between the output of the pulse width modulator and the control input of the charge pump and having an enabling/disabling input connected to the feedback regulator.

26. A method according to claim 21 , further comprising controlling the charge pump based upon the output voltage and the reference voltage with a feedback regulator receiving the output voltage; wherein the pulse signal generator comprises an enabling/disabling unit that defines part of the selection logic unit and is connected to the feedback regulator.

27. A method according to claim 22 , further comprising controlling the charge pump based upon the output voltage and the reference voltage with a feedback regulator receiving the output voltage; wherein the pulse signal generator comprises an enabling/disabling unit that defines part of the selection logic unit and is connected to the feedback regulator.

28. A method according to claim 27 wherein the feedback regulator comprises a comparator having a first input receiving the output voltage, a second input receiving the reference voltage and an output connected to the selection logic unit.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2013
From: STMICROELECTRONICS, S.R.L. (FORMERLY KNOWN AS SGS-THMSON MICROELECTRONICS S.R.L.)
To: MICRON TECHNOLOGY, INC.
Reel/Frame 031796/0348 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2005
From: KHOURI, OSAMA; RAGONE, GIANCARLO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 016286/0535 →