Phase jumping locked loop circuit
A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.
1. An apparatus comprising:
a plurality of differential amplifiers each having inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines; and
a biasing circuit switchably coupled to each of the differential amplifiers, the biasing circuit including a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of differential amplifiers in the plurality of differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of differential amplifiers in the plurality of differential amplifiers,
wherein each transistor of the first plurality of biasing transistors is responsive to a respective bit of a first digital control value to select between a first and a second mode of operation of a selected one of the first set of differential amplifiers,
wherein the first mode of operation enables a current flow within the selected one of the first set of differential amplifiers,
and wherein the second mode of operation disables a current flow within the selected one of the first set of differential amplifiers.
2. The apparatus of claim 1 wherein each transistor of the second plurality of biasing transistors is responsive to a respective bit of a second digital control value to select between a first and a second mode of operation of a selected one of the second set of differential amplifiers, wherein the first mode of operation enables a current flow within the selected one of the second set of differential amplifiers, and wherein the second mode of operation disables a current flow within the selected one of the second set of differential amplifiers.
3. The apparatus of claim 2 wherein the second digital control value is a complement of the first digital control value.
4. The apparatus of claim 1 further comprising a first plurality of switches coupled between the first set of differential amplifiers and the biasing circuit, and a second plurality of switches coupled between the second set of differential amplifiers and the biasing circuit.
5. The apparatus of claim 4 further comprising a select circuit to output a plurality of control signals to the first plurality of switches and the second plurality of switches, the first plurality of switches is responsive to the plurality of control signals to switchably couple a selected differential amplifier of the first set of differential amplifiers to the biasing circuit, and the second plurality of switches is responsive to the plurality of control signals to switchably couple a selected differential amplifier of the second set of differential amplifiers to the biasing circuit.
6. The apparatus of claim 1 wherein at least one of the plurality of differential amplifiers comprises:
a first transistor having a first terminal coupled to a first output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit, and a control terminal coupled to receive a first clock signal of the pair of clock signals; and
a second transistor having a first terminal coupled to a second output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit and to the second terminal of the first transistor, and a control terminal coupled to receive a second clock signal of the pair of clock signals.
7. The apparatus of claim 6 wherein at least one of the first transistor and the second transistor is a bipolar junction transistor.
8. The apparatus of claim 6 wherein at least one of the first transistor and the second transistor is a metal oxide semiconductor (MOS) transistor.
9. The apparatus of claim 1 wherein the biasing circuit further includes a current source coupled in series with the first plurality of biasing transistors and the second plurality of biasing transistors, the current source is biased by a steady-state bias voltage to establish a maximum current through the biasing circuit.
10. An apparatus comprising:
a plurality of differential amplifiers each having inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines;
a biasing circuit switchably coupled to each of the differential amplifiers, the biasing circuit including a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of differential amplifiers in the plurality of differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of differential amplifiers in the plurality of differential amplifiers; and
a select circuit to output a plurality of control signals to a plurality of switches coupled between the plurality of differential amplifiers and the biasing circuit,
wherein each transistor of the first plurality of biasing transistors is responsive to a respective bit of a first digital control value to select between a first and a second mode of operation of a selected one of the first set of differential amplifiers.
wherein the first mode of operation enables a current flow within the selected one of the first set of differential amplifiers,
and wherein the second mode of operation disables a current flow within the selected one of the first set of differential amplifiers.
11. The apparatus of claim 10 wherein each transistor of the second plurality of biasing transistors is responsive to a respective bit of a second digital control value to select between a first and a second mode of operation of a selected one of the second set of differential amplifiers, wherein the first mode of operation enables a current flow within the selected one of the second set of differential amplifiers, and wherein the second mode of operation disables a current flow within the selected one of the second set of differential amplifiers.
12. The apparatus of claim 11 wherein the second digital control value is a complement of the first digital control value.
13. The apparatus of claim 10 wherein the plurality of switches is responsive to the plurality of control signals to switchably couple a selected differential amplifier of the first set of differential amplifiers to the biasing circuit.
14. The apparatus of claim 10 wherein at least one of the plurality of differential amplifiers comprises:
a first transistor having a first terminal coupled to a first output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit, and a control terminal coupled to receive a first clock signal of the pair of clock signals; and
a second transistor having a first terminal coupled to a second output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit and to the second terminal of the first transistor, and a control terminal coupled to receive a second clock signal of the pair of clock signals.
15. An apparatus comprising:
a plurality of differential amplifiers each having inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines; and
a biasing circuit switchably coupled to each of the differential amplifiers, the biasing circuit including a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of differential amplifiers in the plurality of differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of differential amplifiers in the plurality of differential amplifiers; and
a first plurality of switches coupled between the first set of differential amplifiers and the biasing circuit, and a second plurality of switches coupled between the second set of differential amplifiers and the biasing circuit,
wherein at least one of the plurality of differential amplifiers comprises:
a first transistor having a first terminal coupled to a first output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit, and a control terminal coupled to receive a first clock signal of the pair of clock signals; and
a second transistor having a first terminal coupled to a second output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit and to the second terminal of the first transistor, and a control terminal coupled to receive a second clock signal of the pair of clock signals,
wherein each transistor of the first plurality of biasing transistors is responsive to a respective bit of a first digital control value to select between a first and a second mode of operation of a selected one of the first set of differential amplifiers, wherein the first mode of operation enables a current flow within the selected one of the first set of differential amplifiers, and wherein the second mode of operation disables a current flow within the selected one of the first set of differential amplifiers, and
wherein each transistor of the second plurality of biasing transistors is responsive to a respective bit of a second digital control value to select between a first and a second mode of operation of a selected one of the second set of differential amplifiers, wherein the first mode of operation enables a current flow within the selected one of the second set of differential amplifiers, and wherein the second mode of operation disables a current flow within the selected one of the second set of differential amplifiers.
16. The apparatus of claim 15 wherein the second digital control value is a complement of the first digital control value.
17. The apparatus of claim 15 further comprising a select circuit to output a plurality of control signals to the first plurality of switches and the second plurality of switches, the first plurality of switches is responsive to the plurality of control signals to switchably couple a selected differential amplifier of the first set of differential amplifiers to the biasing circuit, and the second plurality of switches is responsive to the plurality of control signals to switchably couple a selected differential amplifier of the second set of differential amplifiers to the biasing circuit.