Integrated circuit
View Patent ↗Embodiments of the present invention relates to an integrated mixer. A problem with producing low power consumption mixers is that they require a relatively high operating voltage due to the number of layers of transistor between the power rails. Accordingly, an embodiment of the present invention provides a mixer comprising first and second double balanced mixers having first and second anti-phase differential RF and LO input signals; the first double balanced mixer having a first set of four active devices each arranged to mix selected pairs of the input signals and to combine the mixed signals via first and second output nodes to produce a first portion of differential intermediate frequency output signals; the second double balanced mixer having a second set of four active devices each arranged to mix selected pairs of the input signals and to combine the mixed signals via the first and second output nodes to produce a second portion of the differential intermediate frequency output signals; the first and second portions of the output signals being combined at the first and second output nodes to produce the differential output signals.
1. A mixer comprising power lines; first and second balanced mixers having RF and anti-phase differential LO input signals; the first balanced mixer having a first set of active devices each arranged to mix selected ones of the input signals and to combine the mixed signals via first and second output nodes to produce a first portion of differential intermediate frequency output signals; the second balanced mixer having a second set of active devices each arranged to mix selected ones of the input signals and to combine the mixed signals via the first and second output nodes to produce a second portion of the differential intermediate frequency output signals; the first and second portions of the output signals being combined at the first and second output nodes to produce the differential output signals, wherein the first balanced mixer, the combination of the first and second output nodes, and the second balanced mixer are arranged in series between the power lines.
2. A mixer as claimed in claim 1 , in which at least one device of at least one of the first and second sets of active devices have a first input terminal and a second input terminal node for receiving respective signals of the selected ones of the input signals.
3. A mixer as claimed in claim 2 , in which the active devices are FETs, and the first input terminal is a gate of a FET and the second input terminal is a well connection of the FET.
4. A mixer as claimed in claim 2 , further comprising at least one biasing resistor for establishing a bias voltage for the second input terminal.
5. A mixer as claimed in claim 2 , further comprising at least one current mirror for biasing the first input terminal.
6. A mixer as claimed in claim 2 , in which the RF input signal is an anti-phase differential RF signal, a first active device (Ti) of the first set of active devices receives a first phase of the RF signal (RF+) and a first phase of the LO signal (LO+) and feeds the mixed pair of signals to the first output node (IF′−).
7. A mixer as claimed in claim 6 , in which a second active device (T 2 ) of the first set of active devices receives a first phase of the RF signal (RF+) and a second phase of the LO input signal (LO−) and feeds the mixed pair of signals to the second output node (IF′+).
8. A mixer as claimed in claim 7 , in which a third active device (T 3 ) of the first set of active devices receives a second phase of the RF signal (RF−) and a second phase of the LO signal (LO−) and feeds the mixed pair of signals to the first output node (IF′−).
9. A mixer as claimed in claim 8 , in which a fourth active device (T 4 ) of the first set of active devices receives a first phase of the RF signal (RF−) and a second phase of the LO signal (LO−)−+) and feeds the mixed pair of signals to the second output node (IF′+).
10. A mixer as claimed in any of claims 2 or 6 , in which the RF input signal is an anti-phase differential signal, a first active device (T 5 ) of the second set of active devices receives a first phase of the RF signal (RF+) and a second phase of the LO signal (LO−) and feeds the mixed pair of signals to the first output node (IF−).
11. A mixer as claimed in claim 10 , in which a second active device (T 6 ) of the second set of active devices receives a first phase of the RF signal (RF+) and a first phase of the LO input signal (LO+) and feeds the mixed pair of signals to the second output node (IF′+).
12. A mixer as claimed in claim 11 , in which a third active device (T 7 ) of the second set of active devices receives a second phase of the RF signal (RF−) and a first phase of the LO signal (LO+) and feeds the mixed pair of signals to the first output node (IF′−).
13. A mixer as claimed in claim 12 , in which a fourth active device (T 8 ) of the second set of active devices receives a second phase of the RF signal (RF−) and a second phase of the LO signal (LO−) and feeds the mixed pair of signals to the second output node (IF+).
14. A mixer as claimed in claim 12 , in which at least one active device (T 6 or T 7 ) of the second set of active devices is biased to maintain the at least one active device in the conducting condition.
15. A mixer as claimed in any of claims 2 or 6 , in which the first set of active devices of the first balanced mixer are p-type devices.
16. A mixer as claimed in claim 10 , in which the second set of active devices of the second balanced mixer are n-type devices.
17. A mixer as claimed in claim 11 , in which the second set of active devices of the second balanced mixer are n-type devices.
18. A mixer as claimed in claim 12 , in which the second set of active devices of the second balanced mixer are n-type devices.
19. A mixer as claimed in claim 13 , in which the second set of active devices of the second balanced mixer are n-type devices.
20. A mixer as claimed in claim 1 , in which the first balanced mixer, the first and second output nodes and the second balanced mixer are arranged in series between power supply rails for the mixer.
21. A mixer comprising power lines; first and second double balanced mixers having first and second anti-phase differential RF and LO input signals; the first double balanced mixer having a first set of four active devices each arranged to mix selected pairs of the input signals and to combine the mixed signals via first and second output nodes to produce a first portion of differential intermediate frequency output signals; the second double balanced mixer having a second set of four active devices each arranged to mix selected pairs of the input signals and to combine the mixed signals via the first and second output nodes to produce a second portion of the differential intermediate frequency output signals; the first and second portions of the output signals being combined at the first and second output nodes to produce the differential output signals, wherein the first balanced mixer, the combination of the first and second output nodes, and the second balanced mixer are arranged in series between the power lines.
22. A mixer as claimed in claim 21 , in which at least one device of at least one of the first and second sets of four active devices have a first input terminal and a second input terminal for receiving respective signals of the selected pairs of the input signals.
23. A mixer as claimed in claim 22 , in which the active devices are FETs, and the first input terminal is a gate of a FET and the second input terminal is a well connection of the FET.
24. A mixer as claimed in claim 22 , further comprising at least one biasing resistor for establishing a bias voltage for the second input terminal.
25. A mixer as claimed in claim 22 , further comprising at least one current mirror for biasing the first input terminal.
26. A mixer as claimed in claim 24 , further comprising at least one current mirror for biasing the first input terminal.
27. A mixer as claimed in claim 22 , in which a first active device (Ti) of the first set of active devices receives a first phase of the RF signal (RF+) and a first phase of the LO signal (LO+) and feeds the mixed pair of signals to the first output node (IF′−).
28. A mixer as claimed in claim 27 , in which a second active device (T 2 ) of the first set of active devices receives a first phase of the RF signal (RF+) and a second phase of the LO input signal (LO−) and feeds the mixed pair of signals to the second output node (IF′+).
29. A mixer as claimed in claim 28 , in which a third active device (T 3 ) of the first set of active devices receives a second phase of the RF signal (RF−) and a second phase of the LO signal (LO−) and feeds the mixed pair of signals to the first output node (IF′−).
30. A mixer as claimed in claim 29 , in which a fourth active device (T 4 ) of the first set of active devices receives a second phase of the RF signal (RF−) and a first phase of the LO signal (LO+) and feeds the mixed pair of signals to the second output node (IF′+).
31. A mixer as claimed in claim 22 , in which a first active device (T 5 ) of the second set of active devices receives a first phase of the RF signal (RF+) and a second phase of the LO signal (LO−) and feeds the mixed pair of signals to the first output node (IF′−).
32. A mixer as claimed in claim 31 , in which a second active device (T 6 ) of the second set of active devices receives a first phase of the RF signal (RF+) and a first phase of the LO input signal (LO−) and feeds the mixed pair of signals to the second output node (IF′+).
33. A mixer as claimed in claim 32 , in which a third active device (T 7 ) of the second set of active devices receives a second phase of the RF signal (RF−) and a first phase of the LO signal (LO+) and feeds the mixed pair of signals to the first output node (IF′−).
34. A mixer as claimed in claim 33 , in which a fourth active device (T 8 ) of the second set of active devices receives a second phase of the RF signal (RF−) and a first phase of the LO signal (LO+) and feeds the mixed pair of signals to the second output node (IF′+).
35. A mixer as claimed in claim 33 , in which at least one active device (T 6 or T 7 ) of the second set of four active devices is biased to maintain the at least one active device in the conducting condition.
36. A mixer as claimed in claim 22 , in which the first set of four active devices of the first double balanced mixer are p-type devices.
37. A mixer as claimed in claim 31 , in which the second set of four active devices of the second double balanced mixer are n-type devices.
38. A mixer as claimed in claim 32 , in which the second set of four active devices of the second double balanced mixer are n-type devices.
39. A mixer as claimed in claim 33 , in which the second set of four active devices of the second double balanced mixer are n-type devices.
40. A mixer as claimed in claim 34 , in which the second set of four active devices of the second double balanced mixer are n-type devices.
41. A mixer as claimed in claim 21 , in which the first double balanced mixer, the first and second output nodes and the second double balanced mixer or the first balanced mixer, the first and second output nodes and the second balanced mixer are arranged in series between power supply rails for the mixer.
42. A mixer as claimed in claim 41 , in which the voltage difference between the power rails is substantially IV.
43. A mixer as claimed in any of claims 1 or 21 , in which the maximum voltage differential between the first and second output nodes is 0.8V.
44. A mixer as clamed in any of claims 21 , 22 , 23 or 41 , in which the first and second sets of active devices each comprise four or two active devices.
45. A mixer as claimed in any of claims 1 or 21 , in which the active devices have two gates for receiving corresponding selected ones of the input signals.
46. A mixer as claimed in any of claims 1 or 21 , in which the active devices have respective gate and well connections for receiving corresponding ones of the input signals.