IP Library Granted Patent US 7,183,786
Granted Patent B2
US 7,183,786 · App. 10/379,178 · Granted Feb 27, 2007

Modifying a semiconductor device to provide electrical parameter monitoring

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Quick Facts
Patent No.
US 7,183,786
App. No.
10/379,178
Granted
Feb 27, 2007
Kind
B2
Abstract

A method of modifying a semiconductor device to provide electrical parameter monitoring. The device includes a semiconductor die and a package substrate. The substrate includes a conductive plane. The die is connected to the plane via a plurality of connection structures. The method includes disconnecting a first one of the connection structures from the plane, and connecting the first connection structure to an external package connection, thereby providing a capability to monitor an electrical parameter of the die via the external package connection.

Claims (26)

1. A method of modifying a semiconductor device to provide electrical parameter monitoring, the device including a semiconductor die and a package substrate, the substrate including a conductive plane, the die connected to the plane via a plurality of connection structures, each of the connection structures separately connecting the die to the plane, the method comprising:

(a) disconnecting a first one of the connection structures from the plane, wherein the disconnected first connection structure remains connected to a power pad or ground pad of the die; and

(b) connecting the disconnected first connection structure to an external package connection of the semiconductor device, thereby providing a capability to monitor an electrical parameter of the die via the external package connection.

2. The method of claim 1 , wherein the conductive plane is a power plane.

3. The method of claim 2 , wherein the power plane is coupled to power pads of the die via the plurality of connection structures, and is coupled to a plurality of power external package connection structures.

4. The method of claim 1 , wherein the conductive plane is a ground plane.

5. The method of claim 4 , wherein the ground plane is coupled to ground pads of the die via the plurality of connection structures, and is coupled to a plurality of ground external package connection structures.

6. The method of claim 1 , wherein the plurality of connection structures are bond wires.

7. The method of claim 1 , wherein the external package connection is a solder structure.

8. The method of claim 1 , wherein the electrical parameter is an internal voltage of the die.

9. The method of claim 1 , wherein the package substrate includes a plurality of conductive planes, and wherein the die is connected to each plane via a plurality of connection structures, the method further comprising:

repeating steps (a) and (b) for each of the conductive planes.

10. A method of measuring an electrical parameter of a semiconductor die, the method comprising:

(a) providing a semiconductor device including a semiconductor die and a package substrate, the substrate including a conductive plane, the die connected to the plane via a plurality of internal package connection structures, each of the internal package connection structures separately connecting the die to the plane;

(b) disconnecting a first one of the internal connection structures from the plane, wherein the disconnected first internal connection structure is connected to a power pad or ground pad of the die;

(c) connecting the disconnected first internal connection structure to a first external package connection structure of the semiconductor device; and

(d) measuring an electrical parameter of the die at the first external connection structure.

11. The method of claim 10 , wherein the conductive plane is a power plane.

12. The method of claim 10 , wherein the conductive plane is a ground plane.

13. The method of claim 11 , wherein the power plane is coupled to power pads of the die via the plurality of internal package connection structures, and is coupled to a plurality of power external package connection structures.

14. The method of claim 12 , wherein the ground plane is coupled to ground pads of the die via the plurality of internal package connection structures, and is coupled to a plurality of ground external package connection structures.

15. The method of claim 10 , wherein the plurality of internal package connection structures are bond wires.

16. The method of claim 10 , wherein the first external package connection structure is a solder structure.

17. The method of claim 10 , wherein the electrical parameter is an internal voltage of the die.

18. The method of claim 10 , wherein the package substrate includes a plurality of conductive planes, and wherein the die is connected to each plane via a plurality of internal package connection structures, the method further comprising:

repeating at least steps (b) and (c) for each of the conductive planes.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
RELEASE OF SECURITY INTEREST Recorded May 15, 2013
From: CITICORP NORTH AMERICA, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030420/0048 →