Defect-free thin and planar film processing
View Patent ↗The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.
1. A process for forming conductive structures on a semiconductor wafer having a top surface with a first feature and a second feature disposed therein, the first feature having a first width and a second feature having the widest width, the process comprising the steps:
electrochemically depositing a first conductive layer to completely fill the first feature and the second feature; and
electrochemically mechanically depositing a second conductive layer over the first conductive layer to form a planar conductive layer.
2. The process of claim 1 , wherein the step of electrochemically depositing includes a first electrolyte solution having a first additive composition and the step of electrochemically mechanically depositing includes a second electrolyte solution having a second additive composition.
3. The process of claim 1 further comprising the step of chemical mechanical polishing the planar conductive layer.
4. The process of claim 1 further comprising the step of electropolishing the planar conductive layer.
5. The process of claim 4 , wherein the step of electropolishing removes substantially all of the planar conductive layer.
6. The process of claim 4 further comprising the step of chemical mechanical polishing the planar conductive layer.
7. The process of claim 6 , wherein the chemical mechanical polishing step removes the second conductive layer from the top surface of the semiconductor wafer.
8. The process of claim 7 , wherein the chemical mechanical polishing step removes the first conductive layer from the top surface of the semiconductor wafer.
9. The process of claim 8 , wherein the chemical mechanical polishing step electrically isolates the first feature from the second feature.
10. The process of claim 1 , wherein the step of electrochemically depositing a first conductive layer deposits the first conductive layer in the second feature to a thickness that is greater than or equal to a depth of the second feature.
11. The process of claim 2 , wherein the step of electrochemically depositing a first conductive layer deposits the first conductive layer in the second feature to a thickness that is greater than or equal to a depth of the second feature.
12. The process of claim 1 further comprising the step of annealing the first conductive layer.
13. The process of claim 1 further comprising the step of annealing the second conductive layer.
14. The process of claim 1 , wherein the first conductive layer and the second conductive layer are copper.