VDDCORE to VSS ESD clamp made of core device
View Patent ↗The present invention comprises an ESD clamp circuit used in an integrated circuit with plural power supply. The ESD clamp circuit, connected between core voltage source and low voltage source, is fabricated by a process which fabricates core circuit. The ESD clamp circuit has a low trigger voltage, so it can conduct large current to protect the core circuit before the core circuit is damaged.
1. An interated circuit, comprising:
a core voltage source;
an input-output voltage source;
a low voltage source;
a core circuit having a first end coupled to the core voltage source and a second end coupled to the low voltage source;
a first clamp circuit having a first end coupled to the core voltage source and a second end coupled to the low voltage source;
a second clamp circuit having a first end coupled to the input-output voltage source and a second end coupled to the core voltage source;
a pad;
a pull up clamp circuit having a first end coupled to the input-output voltage source and a second end coupled to the pad;
a pull down clamp circuit having first end coupled to the pad and a second end coupled to the low voltage source;
wherein the first clamp circuit is fabricated by a process which fabricates the core circuit to avoid an electrostatic discharge current passing through the core circuit; and
wherein the pull up clamp circuit and the pull down clamp circuit are for providing an electrostatic discharge current path.
2. The integrated circuit as claimed in claim 1 , wherein the first clamp circuit comprises a NMOS transistor, which is fabricated by the process which fabricates the core circuit, having thin gate oxide, gate and source both coupled to low voltage source, drain coupled to core voltage source.
3. The integrated circuit as claimed in claim 1 , wherein the first clamp circuit comprises:
a NMOS transistor, which is fabricated by the process which fabricates the core circuit, having thin gate oxide, source coupled to low-voltage, drain coupled to core voltage source;
a resistor connected between the gate of the NMOS transistor and the low voltage source; and
a capacitor connected between the gate of the NMOS transistor and the core voltage source.
4. The integrated circuit as claimed in claim 1 , further comprising a third clamp circuit having a first end coupled to the input-output voltage source and a second end coupled to the low voltage source.
5. An integrated circuit, comprising:
a core voltage source;
an input-output voltage source;
a low voltage source;
a core circuit having a first end coupled to the core voltage source and a second end coupled to the low voltage source;
a first clamp circuit having a first end coupled to the core voltage source and a second end coupled to the low voltage source;
a second clamp circuit having a first end coupled to the input-output voltage source and a second end coupled to the core voltage source; and
a third clamp circuit having a first end coupled to the input-output voltage source and a second end coupled to the low voltage source;
wherein the first clamp circuit is fabricated by a process which fabricates the core circuit to avoid an electrostatic discharge current passing through the core circuit.