Software programmable multiple function integrated circuit module
View Patent ↗An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable function circuits are either interconnected to each other or connected to a plurality of output connectors to transmit manipulated output data signals to external circuitry. The electrically programmable multiple selectable function integrated circuit module has at least one configuration connector, which may be multiplexed with input control and timing signals, connected to a function configuration circuit to receive electrical configuration signals indicating the activation of a program mode and which of the optionally selectable function circuits are to be elected to manipulate the input data signals. The function configuration circuit is connected to the optionally selectable function circuits to selectively elect, which of the optionally selectable function circuits are to is manipulate the input data signals. The electrically programmable multiple selectable function integrated circuit module optionally has common function circuit connected to common function connectors and the plurality of optionally selectable function circuits to manipulate common data signals, and transmit common output data signals to the selectable function circuits.
1. An integrated circuit chip having multiple functional options, comprising:
a function programming circuit comprising a control unit controlling said integrated circuit chip operated in a first mode or in a second mode;
a connection transmitting a first signal when said integrated circuit chip is operated in said first mode, and transmitting a second signal to select one of said multiple functional options when said integrated circuit chip is operated in said second mode, wherein said control unit comprises first and second MOS circuits and an inverter, wherein a channel of said first MOS circuit has said first signal pass therethrough and is connected to said connection, wherein a channel of said second MOS circuit has said second signal pass therethrough and is connected to said connection to select one of said multiple functional options, and wherein a terminal of said inverter is connected to a gate terminal of said first MOS circuit, and another terminal of said inverter is connected to a gate terminal of said second MOS circuit;
a semiconductor substrate;
a redistribution metal over said semiconductor substrate; and
a solder bump connected to an I/O pad of said redistribution metal.
2. The integrated circuit chip of claim 1 , wherein said function programming circuit comprises a latch circuit latching said second signal.
3. The integrated circuit chip of claim 1 , wherein said control unit is controlled by a mode select signal to select said integrated circuit chip operated in said first mode or in said second mode.
4. The integrated circuit chip of claim 1 is a DRAM.
5. A memory chip having multiple data-width options, comprising:
a function programming circuit comprising a control unit controlling said memory chip operated in a first mode or in a second mode;
an address decoder;
an option decoder; and
a connection transmitting a first signal to said address decoder when said memory chip is operated in said first mode, and transmitting a second signal to said option decoder to select one of said multiple data-width options when said memory chip is operated in said second mode, wherein said control unit comprises first and second MOS circuits and an inverter, wherein a channel of said first MOS circuit has said first signal pass therethrough and connects said connection to said address decoder, wherein a channel of said second MOS circuit has said second signal pass therethrough and connects said connection to said option decoder, and wherein a terminal of said inverter is connected to a gate terminal of said first MOS circuit, and another terminal of said inverter is connected to a gate terminal of said second MOS circuit.
6. The memory chip of claim 5 , wherein said function programming circuit comprises a latch circuit latching said second signal.
7. The memory chip of claim 5 , wherein said control unit is controlled by a mode select signal to select said memory chip operated in said first mode or in said second mode.
8. The memory chip of claim 5 is a DRAM.
9. An integrated circuit chip having multiple functional options, comprising:
a function programming circuit comprising a control unit controlling said integrated circuit chip operated in a first mode or in a second mode;
a connection transmitting a first signal when said integrated circuit chip is operated in said first mode, and transmitting a second signal to select one of said multiple functional options when said integrated circuit chip is operated in said second mode, wherein said control unit comprises first and second MOS circuits and an inverter, wherein a channel of said first MOS circuit has said first signal pass therethrough and is connected to said connection, wherein a channel of said second MOS circuit has said second signal pass therethrough and is connected to said connection to select one of said multiple functional options, and wherein a terminal of said inverter is connected to a gate terminal of said first MOS circuit, and another terminal of said inverter is connected to a gate terminal of said second MOS circuit;
a semiconductor substrate; and
a solder bump over said semiconductor substrate.
10. The integrated circuit chip of claim 9 , wherein said function programming circuit comprises a latch circuit latching said second signal.
11. The integrated circuit chip of claim 9 , wherein said control unit is controlled by a mode select signal to select said integrated circuit chip operated in said first mode or in said second mode.
12. The integrated circuit chip of claim 9 is a DRAM.