Top layers of metal for high performance IC's
View Patent ↗A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1. A semiconductor device structure comprising:
a semiconductor substrate comprising semiconductor devices;
an interconnecting metalization structure connected to said devices;
electrical contact points on an upper surface of said interconnecting metalization structure and connected to said interconnecting metalization structure;
a passivation layer deposited over said interconnecting metalization structure and over said electrical contact points;
an insulating layer deposited over said passivation layer said insulating layer being substantially thicker than said passivation layer;
openings through said insulating layer and through said passivation layer down to the upper surface of said electrical contact points;
metal conductors within said openings; and
an upper metalization structure connected to said metal conductors.
2. A semiconductor wafer, comprising:
a semiconductor substrate having an upper passivation layer, through which contact pads are exposed, wherein semiconductor devices are formed on said semiconductor substrate, an interconnecting metallization structure comprising lower metal lines being connected to said devices; and
an upper metallization structure over said passivation layer, connected to said contact pads, comprising upper metal lines, in one or more layers, wherein said upper metal lines are substantially wider than said lower metal lines.
3. The semiconductor wafer of claim 2 , wherein said one or more layers of upper metal lines are separated by organic dielectric layers.
4. The semiconductor wafer of claim 2 , wherein upper contact pads are formed in a top layer of said one or more layers of said upper metal lines.
5. The semiconductor wafer of claim 4 , wherein solder bumps are formed on said upper contact pads.
6. The semiconductor wafer of claim 2 , wherein said upper metallization structure is configured to provide fan-out capabilities comprising:
providing a device having a plurality of contact points thereon; and
connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein a separation between said contact nads is larger than a separation between said contact points.
7. The semiconductor wafer of claim 2 , wherein said upper metallization structure is configured to provide relocation capabilities comprising:
providing a device having a plurality of contact points thereon; and
connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein said connections are in a different sequence from a sequence of said contact points.
8. The semiconductor wafer of claim 2 , wherein said upper metallization structure is configured to provide reduction capabilities comprising:
providing a device having a plurality of contact points thereon; and
connecting each of said plurality of contact points to one or more of said contact pads through said upper metallization structure wherein said contact pads connected are fewer in number said plurality of contact points.
9. A semiconductor wafer, comprising:
a semiconductor substrate having an upper passivation layer, through which contact pads are exposed, wherein semiconductor devices are formed on said semiconductor substrate, an interconnecting metallization structure comprising lower metal lines being connected to said devices; and
an upper metallization structure over said passivation layer, connected to said contact pads, comprising upper metal lines, in one or more layers, wherein said upper metal lines are substantially thicker than said lower metal lines.
10. The semiconductor wafer of claim 9 , wherein said one or more layers of upper metal lines are separated by organic dielectric layers.
11. The semiconductor wafer of claim 9 , wherein upper contact pads are formed in a top layer of said one or more layers of said upper metal lines.
12. The semiconductor wafer of claim 11 , wherein solder bumps are formed on said upper contact pads.
13. The semiconductor wafer of claim 9 , wherein said upper metallization structure is configured to provide fan-out, capabilities comprising:
providing a device having a niurality of contact points thereon: and
connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein a separation between said contact cads is lamer than a separation between said contact points.
14. The semiconductor wafer of claim 13 , wherein said upper metallization structure is configured to provide relocation capabilities comprising:
providing a device having a plurality of contact points thereon; and
connecting each of said plurality of contact points to a contact pad through said upper metallization structure wherein said connections are in a different sequence from a sequence of said contact points.
15. The semiconductor wafer of claim 13 , wherein said upper metallization structure is configured to provide reduction capabilities comprising:
providing a device having a plurality of contact points thereon; and
connecting each of said plurality of contact points to one or more of said contact pads through said upper metallization structure wherein said contact pads connected are fewer in number said plurality of contact points.