Low-power CMOS image device with analog-to-digital converter circuit

1. An analog-to-digital converter circuit comprising:

a comparator for comparing an analog input signal with a reference signal;

an output circuit for generating a digital word indicating a time interval defined by a start signal and an end signal, wherein the end signal indicates a transition of an output of the comparator; and

a controller for inactivating the comparator in response to the end signal.

2. The analog-to-digital converter circuit according to claim 1 , wherein the controller inactivates the comparator when the output of the comparator transitions from an active state to an inactive state.

3. A signal processing circuit which outputs a digital word corresponding to a current source controlled by a physical response, comprising:

an analog integrated circuit for generating an analog signal in response to a time varying reference signal and a signal corresponding to the current source controlled by the physical response;

a reference signal generator for generating a reference signal; a comparator for comparing the analog signal with the reference signal;

an output circuit for generating the digital word indicating a time interval defined by a start signal and an end signal, wherein the end signal indicates a transition of an output of the comparator; and

a controller for inactivating the comparator in response to the end signal.

4. The signal processing circuit according to claim 3 , wherein the controller inactivates the comparator when the output of the comparator transitions from an active state to an inactive state.

5. The signal processing circuit according to claim 4 , wherein the controller comprises, an S-R latch that generates a first enable signal in response to an output of the comparator and a second enable signal, the comparator being inactivated or activate by the first enable signal.

6. The signal processing circuit according to claim 5 , wherein the comparator comprises:

a first transistor having a source connected to a power supply voltage, a drain, and a gate;

a second transistor having a source connected to the power supply voltage, a drain, and a gate connected commonly to the gate and drain of the first transistor;

a third transistor having a drain connected to the drain of the first transistor, a source, and a gate connected to receive the reference signal;

a fourth transistor having a drain connected to the drain of the second transistor, a source connected to the source of the third transistor, and a gate connected to receive the analog signal;

a fifth transistor having a drain connected with a common-source node of the third and fourth transistors, a source, and a gate connected to receive a bias voltage; and

a sixth transistor having a drain connected to the source of the fifth transistor, a source grounded, and a gate connected to receive the first enable signal.

7. The signal processing circuit according to claim 3 , wherein the analog integrated circuit comprises:

a signal generator for generating the signal corresponding to the current source; and

a correlated double sampling signal having a first input terminal connected to receive the signal corresponding to the current source, a second input terminal connected to receive the time varying reference signal, and an output terminal outputting the analog signal.

8. The signal processing circuit according to claim 7 , wherein the correlated double sampling circuit comprises:

a first capacitor connected to the output terminal;

a first switch for selectively connecting the first capacitor and the first input terminal, in response to a first switch control signal; a second capacitor connected to the first capacitor; and

a second switch for selectively connecting the second capacitor and he time varying reference signal, in response to a second switch control signal.

9. The signal processing circuit according to claim 3 , wherein the time varying reference signal is a ramp signal that varies with a predetermined slope according to the start signal.

10. The signal processing circuit according to claim 3 , further comprising a counter that counts cycles of a clock signal in response to a counter enable signal, wherein the output circuit generates an output of the counter s the digital word when an output of the comparator transitions from an active level to an inactive level.

11. A method for performing analog-to-digital conversion in a CMOS image device, the method comprising the steps of:

generating an analog signal in response to a time varying reference signal and a voltage of column data line of a sensor array;

comparing the analog signal with a reference signal and outputting a comparing signal based on the result of the comparing;

outputting a digital word to the image device when the comparing signal transition from a first state to a second state; and

suspending the comparing step upon said transition of the comparing signal.

12. The method according to claim 11 , wherein the time varying reference signal is a ramp signal that varies with a predetermined slope.

13. The method according to claim 11 , further comprising the step of activating the comparing step in response to a compare enable control signal.

14. The method according to claim 13 , wherein the compare enable control signal is activated during a reset sampling period in which a sensor voltage is reset or a sensor in a selected row of the array.