Semiconductor circuit device adaptable to plurality of types of packages
View Patent ↗Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.
1. A semiconductor circuit device comprising:
internal circuitry including memory cells storing data and formed on a semiconductor chip; and
a plurality of pads arranged around the chip in an external region of said internal circuitry, said plurality of pads including a plurality of data pads arranged being distributed into outer peripheral portions of at least four divided regions of said chip and selectively used in each of the divided regions in accordance with a word structure of data inputted and outputted by said internal circuitry.
2. The semiconductor circuit device according to claim 1 , wherein
said chip has a rectangular shape, and
said plurality of data pads are arranged being distributed along opposite two sides of said chip.
3. The semiconductor circuit device according to claim 1 , wherein
said plurality of pads include power source pads arranged corresponding to the data pads arranged being distributed into said four divided regions, and
the data pads and power source pads are made different in number to be used in each divided region for a different word structure, and are so thinned out to be used, when the word structure is different from a maximum permitted number of bits, that an unused pad is arranged between used pads in each divided region.
4. The semiconductor circuit device according to claim 1 , wherein
said internal circuitry includes a plurality of memory circuits, arranged in the respective four divided regions, each for storing the data, and
said semiconductor circuit device further comprises:
a plurality of data buses for coupling the memory circuits and said plurality of data pads, load capacitance of each respective data bus being equal to load capacitance of other data bus.
5. The semiconductor circuit device according to claim 1 , wherein
said internal circuitry includes a memory selecting circuit for accessing said memory cells,
said semiconductor circuit device further comprises:
a compression circuit for compressing and outputting memory cell data read out simultaneously from said memory selecting circuit in a test operation mode; and
a connection control circuit for establishing connection between an output of said compression circuit and said plurality of data pads in accordance with a word structure instruction signal indicating the word structure.
6. The semiconductor circuit device according to claim 1 , wherein
said chip has a rectangular shape, and
said plurality of data pads are arranged being distributed along opposite two sides of said chip, the data pads arranged being distributed into said four divided regions are used in accordance with the word structure upon assembly into a first package, and the data pads arranged being distributed along one of the two sides are selectively used in accordance with said word structure upon assembly into a second package.
7. The semiconductor circuit device according to claim 1 , further comprising:
a plurality of data bus lines arranged corresponding to said plurality of data pads, wherein
said plurality of data bus lines are arranged such that an unused data bus line is arranged between the data bus lines to be used in accordance with said word structure.