Semiconductor device without adverse effects caused by inclinations of word line and bit line
View Patent ↗The inclination of a word line near asymmetrical contacts is improved by providing an extending portion between the contact and the word line in a DRAM cell array pattern having the asymmetrical contact at an end portion of the word line extending in one direction. The extending portion is provided symmetrically to the word line or is provided on the opposed side of the extending direction of the asymmetrical contact. Alternatively, the extending portion is provided for a bit line as well as the word line.
1. A semiconductor device comprising a word line, a bit line, and a storage node adjacent to said word line and said bit line;
at least one of said word line and said bit line having a planar pattern extending substantially perpendicular to at least one of said word line and said bit line and extending between at least one of said word line and said bit line and said storage node for preventing inclination at an end portion of at least one of said word line and said bit line.
2. A semiconductor device according to claim 1 , wherein said planar pattern provided for at least one of said word line and said bit line is structured by an extending portion having an equal shape on both sides of at least one of said word line and said bit line.
3. A semiconductor device according to claim 2 , wherein said extending portion has a rectangular shape.
4. A semiconductor device according to claim 2 , wherein said extending portion has a taper shape which is symmetrical on both sides thereof.
5. A semiconductor device according to claim 2 , wherein said extending portion is provided at a boundary portion between a dummy cell portion and a contact portion for connecting a word driver.
6. A semiconductor device comprising a memory cell area including a plurality of memory cells and two word driver areas for sandwiching said memory cell area from both opposed sides;
said memory area comprising:
a plurality of word lines which extend in a single direction between said two word driver areas;
a bit line which extends in the direction crossing to said word line; and
a contact portion for the word driver arranged to each of said word driver areas and connected to every other word line, which is asymmetrical to said word line;
said device further comprising a planar pattern, for preventing the inclination of said word line caused by said asymmetrical contact portion for the word driver, arranged at a position adjacent to the contact portion for the word driver of said word line between said word line and said contact portion, substantially perpendicular to said word line.
7. A semiconductor device according to claim 6 , wherein said asymmetrical contact portion for the word driver has a shape projecting to one side of the corresponding word line;
said planar pattern having at least an extending portion which extends from said word line to the opposed side.
8. A semiconductor device comprising a memory cell area including a plurality of memory cells, and two word driver areas which sandwiches said memory cell area from both opposed sides;
said memory area comprising:
a plurality of word lines which extend in a single direction between said two word driver areas, said semiconductor device structured and arranged so that a width of each of said plural word lines is not larger than 0.15 μm;
a bit line which extends in the direction crossing to said word line; and
a contact portion for the word driver arranged to each of said word driver areas and connected to every other word line;
said contact portion for the word driver of said word line having a shape symmetrical to said word line;
said semiconductor device thus preventing the inclination of said word line.
9. A semiconductor device comprising an electrode wiring and a signal transfer wiring;
at least one of said electrode and said signal transfer wirings having an asymmetrical pattern with a shape asymmetrical to an extending direction of said wirings;
said device further comprising a planar pattern comprising a portion symmetrically extending from and substantially perpendicular to an extending direction of at least one of said electrode and said signal transfer wirings;
said device preventing that stress caused by the symmetrical pattern in the manufacturing process of the semiconductor device affects to at least one of said electrode and said signal transfer wirings as an end portion of said planar pattern.