Triple-well charge pump stage with no threshold voltage back-bias effect

1. A charge pump stage comprising:

a first n-channel transistor having a source coupled to an input terminal and a drain coupled to an output terminal;

a second n-channel transistor having a source coupled to the input terminal, a drain coupled to a gate of the first n-channel transistor, and a gate coupled to the output terminal;

a third n-channel transistor having a source coupled to the input terminal, a gate coupled to the output terminal, and a drain coupled to a p-well;

a fourth n-channel transistor having a source coupled to the output terminal, a gate coupled to the input terminal, and a drain coupled to the p-well, wherein the first, second, third and fourth n channel transistors are fabricated in the p-well;

a first capacitor coupled to the output terminal; and

a second capacitor coupled to the gate of the first n-channel transistor.

2. The charge pump stage of claim 1 , further comprising:

a first clock terminal for receiving a first clock signal, wherein the first capacitor is coupled between the output terminal and the first clock terminal; and

a second clock terminal for receiving a second clock signal, wherein the second capacitor is coupled between the gate of the first n-channel transistor and the second clock terminal.

3. The charge pump stage of claim 1 , further comprising:

an n-well surrounding the p-well; and

a p-type region surrounding the n-well.

4. The change pump stage of claim 1 , further comprising:

a second well region surrounding the first well region, wherein the first and second well regions have different conductivity types; and

a third well region surrounding the second well region, wherein the second and third well regions have different conductivity types.

5. A charge pump circuit comprising:

a first charge pump stage that includes:

a first n-channel transistor having a source coupled to a first input terminal and a drain coupled to a first output terminal;

a second n-channel transistor having a source coupled to the first input terminal, a drain coupled to a gate of the first n-channel transistor, and a gate coupled to the first output terminal;

a third n-channel transistor having a source coupled to the first input terminal, a gate coupled to the first output terminal, and a drain coupled to a first p-well;

a fourth n-channel transistor having a source coupled to the first output terminal, a gate coupled to the first input terminal, and a drain coupled to the first p-well, wherein the first, second, third and fourth n-channel transistors are fabricated in the first p-well;

a first capacitor coupled to the first output terminal; and

a second capacitor coupled to the gate of the first n-channel transistor; and

a second charge pump stage that includes:

a fifth n-channel transistor having a source coupled to the first output terminal and a drain coupled to a second output terminal;

a sixth n-channel transistor having a source coupled to the first output terminal, a drain coupled to a gate of the fifth n-channel transistor, and a gate coupled to the second output terminal;

a seventh n-channel transistor having a source coupled to the first output terminal, a gate coupled to the second output terminal, and a drain coupled to a second p-well;

a eighth n-channel transistor having a source coupled to the second output terminal, a gate coupled to the first output terminal, and a drain coupled to the second p-well, wherein the fifth, sixth, seventh and eighth n-channel transistors are fabricated in the second p-well;

a third capacitor coupled to the second output terminal; and

a fourth capacitor coupled to the gate of the fifth n-channel transistor.

6. The charge pump circuit of claim 5 , further comprising:

a first clock terminal for receiving a first clock signal, wherein the first capacitor is coupled between the first output terminal and the first clock terminal;

a second clock terminal for receiving a second clock signal, wherein the second capacitor is coupled between the gate of the first n-channel transistor and the second clock terminal;

a third clock terminal, for receiving a third clock signal, wherein the third capacitor is coupled between the second output terminal and the third clock terminal; and

a fourth clock terminal for receiving a fourth clock signal, wherein the fourth capacitor is coupled between the gate of the fifth n-channel transistor and the fourth clock terminal.

7. The charge pump circuit of claim 5 , further comprising:

an n-well surrounding the first p-well and the second p-well; and

a p-type region surrounding the n-well.

8. A charge pump stage comprising:

a first transistor having a source coupled to an input terminal and a drain coupled to an output terminal;

a second transistor having a source coupled to the input terminal, a drain coupled to a gate of the first transistor, and a gate coupled to the output terminal;

a third transistor having a source coupled to the input terminal, a gate coupled to the output terminal, and a drain coupled to a well region;

a fourth transistor baying a source coupled to the output terminal, a gate coupled to the input terminal, and a drain coupled to the well region, wherein the first and second transistors are fabricated in the well region;

a first capacitor coupled to the output terminal; and

a second capacitor coupled to the gate of the first transistor.

9. The charge pump stage of claim 8 , further comprising:

a first clock terminal for receiving a first clock signal, wherein the first capacitor is coupled between the output terminal and the first clock terminal; and

a second clock terminal for receiving a second clock signal, wherein the second capacitor is coupled between the gate of the first transistor and the second clock terminal.