Program counter circuit
View Patent ↗A program counter circuit is composed of two kinds of registers, a down counter, an up counter, a selector, and a logic circuit. The two kinds of registers hold a pre-jump PC value and a post-jump PC value of a jump that is prescribed by a program. The down counter holds the number of repetitions of a repeat sequence that is prescribed by the program. The up counter holds a PC value that is counted up for each clock pulse. The selector selects, as a PC value to be output next, the post-jump PC value or the value that is held by the up counter. The logic circuit refers to the output value of the program counter and the output values of the registers and the down counter, and generates a signal that instructs the selector what PC value should be selected as the next output value.
1. A program counter circuit comprising:
an up counter for holding, in an initial state, a prescribed initial value of a first PC value, outputting the first PC value for each reference clock pulse, and counting up a feedback value of the output first PC value and holding a resulting count-up value;
at least one pre-jump PC register for holding, as a second PC value, a pre-jump PC value of a jump that is prescribed by a program, and for outputting the second PC value for each reference clock pulse;
at least one post-jump register for holding, as a third PC value, a post-jump PC value of the jump, and for outputting the third PC value for each reference clock pulse;
at least one down counter for holding a value indicating the number of repetitions of a repeat sequence that is prescribed by the program, outputting the value for each reference clock pulse, and counting down a feedback value of the output value when receiving a prescribed subtraction instruction signal and holding a resulting count-down value;
a selector for selecting one of the first PC value that is output from the up counter and the third PC value that is output from the post-jump PC register, and for outputting the selected PC value as an output PC value of the program counter circuit; and
a logic circuit coupled to the selector, the up counter, the pre-jump PC register, the post-jump PC register, and the down counter, for providing a logic that causes the selector to select the third PC value if the output PC value of the selector coincides with the first PC value that is output from the pre-jump PC register and the output value of the down counter is not a value indicating that the number of repetitions is 0, and to select the first PC value in the other cases.
2. The program counter circuit according to claim 1 , wherein the program counter circuit comprises a plurality of down counters, the program counter circuit further comprising a counter designation register for setting an identifier that indicates desired one of the plurality of down counters.
3. The program counter circuit according to claim 1 , wherein the logic circuit comprises:
a first comparator for comparing the output PC value that is output from the selector with the first PC value that is output from the pre-jump PC register, and for outputting a first judgment value indicating whether the output PC value and the first PC value coincide with each other;
an AND circuit for ANDing the first judgment value and the output value of the down counter;
a second comparator for comparing an output of the AND circuit with a prescribed comparison reference value, and for outputting a second judgment value indicating whether the output of the AND circuit coincides with the prescribed comparison reference value; and
an output control unit that receives the first judgment value and the second judgment value, for sending the selector an instruction signal that instructs the selector to select the third PC value if the first judgment value indicates coincidence and the second judgment value indicates non-coincidence and, in the other cases, sending the selector an instruction signal that instructs the selector to select the first PC value.
4. The program counter circuit according to claim 1 , wherein the down counter is a linear feedback shift register.
5. The program counter circuit according to claim 1 , further comprising an initial value setting circuit for setting an arbitrary initial value in the up counter.