Mixed signal delay locked loop characterization engine
View Patent ↗A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop using a top-down approach in order to ensure the robustness of the mixed signal delay locked loop. Top-level testing involves testing the performance of the mixed signal delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the mixed signal delay locked loop.
1. A method for characterizing a mixed signal delay locked loop, comprising:
top-level testing the mixed signal delay locked loop to generate a waveform representative of an operation of the mixed signal delay locked loop, wherein the top-level testing involves at least one of the following:
adjusting a phase of a reference clock, adjusting a freciuency of the reference clock, adjusting a duty cycle of the reference clock, and adjusting relationships of differential inputs to the mixed signal delay locked loop;
bottom-level testing at least one of the digital sub-circuits in the mixed signal delay locked loop; and
bottom-level testing at least one of the analog sub-circuits in the mixed signal delay locked loop.
2. The method of claim 1 , wherein the bottom-level testing of the at least one of the analog sub circuits is dependent on the waveform.
3. The method of claim 1 , further comprising binary input data to piece-wise linear data.
4. The method of claim 1 , wherein the top-level testing comprises:
inputting a circuit schematic of the mixed signal delay locked loop;
inputting configuration information descriptive of at least one signal associated with the mixed signal delay locked loop; and
simulating the mixed signal delay locked loop in at least one process corner using the circuit schematic and configuration information.
5. The method of claim 1 , wherein the top-level testing comprises at least one selected from the group consisting adjusting a phase of an input to the mixed signal delay locked loop, adjusting a frequency of the input to the mixed signal delay locked loop, and adjusting a duty cycle of the input to the mixed signal delay locked loop.
6. The method of claim 1 , wherein the top-level testing is performed at a plurality of process corners.
7. The method of claim 1 , further comprising:
analyzing the circuit by applying the waveform to an input of the mixed signal delay locked loop.
8. The method of claim 1 , wherein the top-level testing comprises:
applying a test value to one selected from the group consisting a reference clock input to the mixed signal delay locked loop, a reset signal to the mixed signal delay locked loop, a control voltage of the mixed signal delay locked loop, a power signal to the mixed signal delay locked loop, and an output clock of the mixed signal delay locked loop; and
storing the waveform, wherein the waveform is determined based on the applying.
9. A computer-readable medium having recorded therein instructions executable by processing the instructions for:
top-level testing a mixed signal delay locked loop to generate a waveform representative of an operation of the mixed signal delay locked loop, wherein the top-level testing involves at least one of the following:
adjusting a phase of a reference clock, adjusting a frequency of the reference clock, adjusting a duty cycle of the reference clock, and adjusting relationships of differential inputs to the mixed signal delayed locked loop;
bottom-level testing at least one of the digital sub-circuits in the mixed signal delay locked loop; and
bottom-level testing at least one of the analog sub-circuits in the mixed signal delay locked loop.
10. The computer-readable medium of claim 9 , further comprising instructions for transforming binary input data to piece-wise linear input data.
11. The computer-readable medium of claim 9 , wherein the instructions for the bottom-level testing of the at least one of the analog sub-circuits are dependent on the waveform.
12. The computer-readable medium of claim 9 , wherein the instructions for the top-level testing comprise instructions for at least one selected from the group consisting adjusting a phase of an input to the mixed signal delay locked loop, adjusting a frequency of the input to the mixed signal delay locked loop, and adjusting a duty cycle of the input to the mixed signal delay locked loop.
13. The computer-readable medium of claim 9 , wherein the top-level testing is performed at a plurality of process corners.
14. The computer-readable medium of claim 9 , wherein the instructions for the top-level testing comprise instructions for:
applying a test value to one selected from the group consisting a reference clock input to the mixed signal delay locked loop, a reset signal to the mixed signal delay locked loop, a control voltage of the mixed signal delay locked loop, a power signal to the mixed signal delay locked loop, and an output clock of the mixed signal delay locked loop; and
storing the waveform, wherein the waveform is determined based on the applying.
15. A computer system, comprising:
a processor;
a memory; and
instructions, residing in the memory and executable by the processor, for top-level testing a mixed signal delay locked loop to generate a waveform representative of an operation of the mixed signal delay locked loop, wherein the top-level testing involves adjusting a phase of a reference clock, adjusting a freciuency of the reference clock, adjusting a duty cycle of the reference clock, and adjusting relationships of differential inputs to the mixed signal delay locked loop, bottom-level testing at least one of the digital sub-circuits in the mixed signal delay locked loop, and bottom-level testing at least one of the analog sub-circuits in the mixed signal delay locked loop.
16. The computer system of claim 15 , further comprising instructions for:
applying a test value to one selected from the group consisting a reference clock input to the mixed signal delay locked loop, a reset signal to the mixed signal delay locked loop, a control voltage of the mixed signal delay locked loop, a power signal to the mixed signal delay locked loop, and an output clock of the mixed signal delay locked loop; and
storing the waveform, wherein the waveform is determined based on the applying.
17. The computer system of claim 15 , further comprising instructions transforming binary input data to piece-wise linear input data.