Dual function clock signal suitable for host control of synchronous and asynchronous target devices
View Patent ↗A host device in a data communication system provides a dual-function clock/enable signal at a single output port shared by at least one asynchronous target device and at least one synchronous target device. In the asynchronous operating mode, the host device generates an asynchronous gated-clock signal that facilitates read/write functions of one or more selected asynchronous target devices. In the synchronous operating mode, the host device generates a synchronous clock-gate signal that facilitates read/write functions of one or more selected synchronous target devices. The target devices and the host device share both a common data bus and a common clock bus. The host device supplies the dual-function clock/enable signal on the common clock bus.
1. A method for generating a clock signal by a host device that supports a plurality of target devices, said method comprising:
generating, in a first operating mode, an asynchronous gated-clock signal onto a common clock bus shared by said plurality of target devices; and
generating, in a second operating mode, a synchronous clock-gate signal onto said common clock bus.
2. A method according to claim 1 , further comprising providing, in said second operating mode, a reference clock signal having a period that influences timing characteristics of said synchronous clock-gate signal.
3. A method according to claim 1 , further comprising transferring, in said first operating mode and in response to said asynchronous gated-clock signal, a data set between said host device and an asynchronous target device.
4. A method according to claim 3 , wherein transferring said data set is performed in response to a rising edge of said asynchronous gated-clock signal.
5. A method according to claim 1 , further comprising transferring, in said second operating mode and in response to said synchronous clock-gate signal, a data set between said host device and a synchronous target device.
6. A method according to claim 5 , wherein transferring said data set is performed in response to a rising edge of a reference clock signal.
7. A method according to claim 6 , wherein transferring said data set is performed when said synchronous clock-gate signal represents a data enable state.
8. A method according to claim 1 , further comprising:
selecting a current target device from said plurality of target devices;
enabling said current target device;
if said current target device is an asynchronous target device, providing said asynchronous gated-clock signal to said current target device; and
if said current target device is a synchronous target device, providing said synchronous clock-gate signal to said current target device.
9. A method of controlling data transfer between a host device and a plurality of target devices including one or more asynchronous target devices and one or more synchronous target devices, said host device and said plurality of target devices sharing a common data bus and a common clock bus, said method comprising:
in a first operating mode,
enabling at least one asynchronous target device to facilitate data transfer with said host device;
said host device generating an asynchronous gated-clock signal onto said common clock bus; and
transferring a data set between said host device and said at least one asynchronous target device in response to said asynchronous gated-clock signal; and
in a second operating mode,
enabling at least one synchronous target device to facilitate data transfer with said host device;
said host device generating a synchronous clock-gate signal onto said common clock bus; and
transferring a data set between said host device and said at least one synchronous target device in response to said synchronous clock-gate signal.
10. A method according to claim 9 , further comprising:
in said first operating mode, disabling said synchronous target devices; and
in said second operating mode, disabling said asynchronous target devices.
11. A method according to claim 9 , wherein:
in said first operating mode, transferring said data set represents a host read operation or a host write operation; and
in said second operating mode, transferring said data set represents a host read operation or a host write operation.
12. A method according to claim 9 , further comprising:
providing, in said second operating mode, a reference clock signal having a period that influences timing characteristics of said synchronous clock-gate signal.
13. A method according to claim 12 , wherein, in said second operating mode, transferring said data set is responsive to a rising edge of said reference clock signal.
14. A method according to claim 13 , wherein, in said second operating mode, transferring said data set is performed when said synchronous clock-gate signal represents a data enable state.
15. A method according to claim 9 , wherein, in said first operating mode, transferring said data set is responsive to a rising edge of said asynchronous gated-clock signal.
16. A data communication apparatus comprising:
a common clock bus output;
a signal generator arrangement configured to produce a synchronous clock-gate signal and an asynchronous gated-clock signal;
a signal selector coupled to said signal generator arrangement and to said common clock bus output; and
a controller that governs selection of either said synchronous clock-gate signal or said asynchronous gated-clock signal for provision at said common clock bus output.
17. A data communication apparatus according to claim 16 , further comprising a reference clock generator configured to produce a reference clock signal having a period that influences timing characteristics of said synchronous clock-gate signal.
18. A data communication apparatus according to claim 16 , further comprising a common data bus output configured to facilitate data transfer between said apparatus and a plurality of target devices including one or more asynchronous target devices and one or more synchronous target devices.
19. A data communication apparatus according to claim 18 , wherein:
said controller is further configured to control, in a first operating mode and in response to said asynchronous gated-clock signal, data transfer between said apparatus and an asynchronous target device; and
said controller is further configured to control, in a second operating mode and in response to said synchronous clock-gate signal, data transfer between said apparatus and a synchronous target device.
20. A data communication apparatus comprising:
a common clock bus;
means for generating, in a first operating mode, an asynchronous gated-clock signal onto said common clock bus for use by one or more asynchronous target devices; and
means for generating, in a second operating mode, a synchronous clock-gate signal onto said common clock bus for use by one or more synchronous target devices.