Current drive circuit avoiding effect of voltage drop caused by load and semiconductor memory device equipped therewith

1. A current drive circuit passing a current through a load circuit with resistance, comprising:

a node connected to said load circuit; and

a driver receiving a first voltage and a second voltage; wherein

a voltage difference between said second voltage and a voltage on said node is larger than a voltage difference between said first voltage and the voltage on said node; and

said driver passes a current through said node in accordance with said voltage difference between said second voltage and the voltage on said node.

2. The current drive circuit according to claim 1 , further comprising

a precharge circuit precharging said node to a third voltage when a current does not pass through said node.

3. The current drive circuit according to claim 1 , wherein

said driver includes a transistor receiving either one of said first or second voltage at one terminal, with other terminal connected to said node.

4. The current drive circuit according to claim 3 , wherein

said driver further includes a voltage supplying circuit; and wherein

said voltage supplying circuit receives said first and second voltages, and supplies said first voltage to said transistor when the current drive circuit is deactivated, and supplies said second voltage to said transistor when the current drive circuit is activated.

5. The current drive circuit according to claim 3 , further comprising a control circuit controlling an operation of the current drive circuit in accordance with an operating mode, wherein

said operating mode is any one of

an inactive mode in which said first voltage is applied to said one terminal of said transistor

a standby mode in which said transistor is in an off state when said second voltage is applied to said one terminal of said transistor; and

an active mode in which said transistor is in an on state when said second voltage is applied to said one terminal of said transistor; wherein

said control circuit controls

an operation of said transistor based on a first operating voltage when said operating mode is said inactive mode; and

an operation of said transistor based on a second operating voltage when said operating mode is either said standby mode or said active mode; and wherein

a voltage difference between said second operating voltage and said second voltage is smaller than a voltage difference between said second voltage and said first operating voltage.

6. The current drive circuit according to claim 5 , wherein

said first operating voltage is made of a first supply voltage and a first ground voltage,

said second operating voltage is made of a second supply voltage and a second ground voltage,

a voltage difference between said second voltage and said second supply voltage is smaller than a voltage difference between said second voltage and said first supply voltage,

a voltage difference between said second voltage and said second ground voltage is smaller than a voltage difference between said second voltage and said first ground voltage, and

said control circuit, when said operating mode is said inactive mode, outputs a first gate voltage turning said transistor on and a second gate voltage turning said transistor off based on said first supply voltage and said first ground voltage, and when said operating mode is either said standby mode or said active mode, outputs said first and second gate voltages based on said second supply voltage and said second ground voltage.

7. The current drive circuit according to claim 6 , wherein

said driver further includes another transistor,

said transistor is connected between a power supply node and said node for supplying electrical charges to said node,

said another transistor is connected between said node and a ground node for discharging electrical charges from said node;

said transistor is configured with an N-channel MOS transistor, and

said second supply voltage is set higher than said second voltage.

8. A semiconductor memory device, comprising:

a plurality of memory cells arranged in rows and columns;

a plurality of bit lines provided corresponding to each column of memory cells; and

a plurality of current drive circuits provided corresponding to said plurality of bit lines, passing a current through corresponding bit line; wherein

each of said plurality of current drive circuits receives a first voltage and a second voltage, a voltage difference between said second voltage and a voltage on said corresponding bit line is larger than a voltage difference between said first voltage and the voltage on said corresponding bit line, and each of said plurality of current drive circuits passes a current through said corresponding bit line in accordance with said voltage difference between said second voltage and the voltage on said corresponding bit line.

9. The semiconductor memory device according to claim 8 , further comprising

a voltage supply circuit receiving said first and second voltages, and when the semiconductor memory device is deactivated, supplying said first voltage to said plurality of current drive circuits, and when the semiconductor memory device is activated, supplying said second voltage to said plurality of current drive circuits.

10. The semiconductor memory device according to claim 8 , further comprising

a plurality of precharge circuits provided corresponding to said plurality of bit lines, and when a current does not pass through corresponding bit line, precharging said corresponding bit line to a third voltage.

11. The semiconductor memory device according to claim 10 , wherein

each of said plurality of current drive circuits includes

a first transistor connected between said corresponding bit line and a power supply node, and supplying electrical charges to said corresponding bit line, and

a second transistor connected between said corresponding bit line and a ground node, and discharging electrical charges of said corresponding bit line.

12. The semiconductor memory device according to claim 11 , wherein

said third voltage is at a same voltage level with a gate voltage and said first voltage applied to a gate of said first transistor and said power supply node, respectively, in the current drive circuit when the current drive circuit is deactivated.

13. The semiconductor memory device according to claim 11 , wherein

each of said plurality of current drive circuits further includes a control circuit controlling an operation of said first and second transistors, and

said control circuit, when the current drive circuit is activated, controls an operation of said first transistor based on an operating voltage higher than when the current drive circuit is deactivated.

14. The semiconductor memory device according to claim 11 , wherein

said second transistor, when the current drive circuit is activated, receives a fourth voltage lower than a ground voltage from said ground node.

15. The semiconductor memory device according to claim 8 , wherein

each of said plurality of bit lines has its opposing ends connected to one of said current drive circuits, respectively,

two adjacent bit lines among said plurality of bit lines have their one ends connected to each other, and share one of said current drive circuits connected to said connected one ends.

16. The semiconductor memory device according to claim 8 , wherein

each of said plurality of memory cells includes a resistor element, of which resistance value is determined in accordance with stored data, and which stores a data in accordance with said resistance value.