IP Library Granted Patent US 7,045,383
Granted Patent B2
US 7,045,383 · App. 10/396,587 · Granted May 16, 2006

Method for making tapered opening for programmable resistance memory element

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Quick Facts
Patent No.
US 7,045,383
App. No.
10/396,587
Granted
May 16, 2006
Kind
B2
Abstract

A method for making a tapered opening. The defined tapered opening is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide.

Claims (63)

1. A method of fabricating a second opening, comprising:

providing a layer of a first material;

forming a layer of a second material over said layer of said first material;

forming a layer of a third material over said layer of said second material;

forming a first opening in said layer of said third material to expose said second material, said first opening not extending into substantially any of said layer of said second material;

forming a sidewall spacer of a fourth material on a sidewall surface of said first opening;

removing a first portion of said layer of said second material to form a recess in said layer of said second material, said recess does not expose said first material, said recess having a bottom surface consisting essentially of the same material as said first portion of said second material; and

removing a second portion of said second material to form said second opening in said layer of said second material exposing said first material.

2. The method of claim 1 , wherein said second opening is a hole.

3. The method of claim 1 , wherein said second opening is a trench.

4. The method of claim 1 , wherein said third material and said fourth material are the same material.

5. The method of claim 1 , wherein said first material is a conductive material.

6. The method of claim 1 , wherein said second material is a dielectric.

7. The method of claim 6 , wherein said dielectric comprises an oxide or a nitride.

8. The method of claim 1 , wherein said third material and said fourth material are polysilicon.

9. The method of claim 1 , wherein said third material and said fourth material are a dielectric.

10. The method of claim 9 , wherein said dielectric is an oxide or a nitride.

11. The method of claim 1 , wherein the ratio of the depth of said recess of said second layer to the thickness of said second layer is less than 0.5.

12. The method of claim 1 , further comprising, after said recess is formed, removing at least a portion of said sidewall spacer so as to decrease the thickness of said spacer.

13. The method of claim 1 , further comprising removing at least a portion of said sidewall spacer so as to decrease the thickness of said spacer while removing said second portion of said second material.

14. The method of claim 13 , wherein the rate of removal of said sidewall spacer is greater than the rate of removal of said second portion of said second material.

15. The method of claim 1 , further comprising removing a third portion of said second material from a sidewall surface of said recess while removing said second portion of said second material.

16. The method of claim 13 , further comprising removing a third portion of said second material from a sidewall surface of said recess while removing said second portion of said second material.

17. A method of fabricating a memory element, comprising:

providing a layer of a first material;

forming a layer of said second material over said layer of said first material;

forming a layer of a third material over said layer of said second material; forming a first opening in said layer of said third material to expose said second material, said first opening not extending into substantially any of said layer of said second material;

forming a sidewall spacer of a fourth material on a sidewall surface of said first opening;

removing a first portion of said second material to form a recess in said layer of said second material, said recess does not expose said first material, said recess having a bottom surface consisting essentially of the same material as said first portion of said second material;

removing a second portion of said layer of said second material to form a second opening in said layer of said second material exposing said first material; and

forming a programmable resistance material in said second opening of said second material.

18. The method of claim 17 , wherein said second opening in said layer of said second material is a hole.

19. The method of claim 17 , wherein said second opening in said layer of said second material is a trench.

20. The method of claim 17 , wherein said third material and said fourth material are the same material.

21. The method of claim 17 , wherein said first material is a conductive material.

22. The method of claim 17 , wherein said second material is a dielectric material.

23. The method of claim 22 , wherein said dielectric is an oxide or a nitride.

24. The method of claim 17 , wherein said third material and said fourth material are polysilicon.

25. The method of claim 17 , wherein said third material and said fourth material are a dielectric.

26. The method of claim 25 , wherein said dielectric is an oxide or a nitride.

27. The method of claim 17 , wherein the ratio of the depth of said recess of said second layer to the thickness of said second layer is less thin 0.5.

28. The method of claim 17 , further comprising forming a conductive material over said programmable resistance material after forming said programmable resistance material.

29. The method of claim 17 , wherein said programmable resistance material is in direct contact with said first material.

30. The method of claim 17 , wherein said programmable resistance material is a phase-change material.

31. The method of claim 17 , further comprising, after said recess is formed, removing at least a portion of said sidewall spacer so as to decrease the thickness of said spacer.

32. The method of claim 17 , further comprising removing at least a portion of said sidewall spacer so as to decrease the thickness of said spacer while removing said second portion of said second material.

33. The method of claim 32 , wherein the rate of removal of said sidewall spacer is greater than the rate of removal of said second portion of said second material.

34. The method of claim 17 , further comprising removing a third portion of said second material from a sidewall surface of said recess while removing said second portion of said second material.

35. The method of claim 32 , further comprising removing a third portion of said second material from a sidewall surface of said recess while removing said second portion of said second material.

36. A method of fabricating an electrical device, comprising:

providing a layer of a first material;

forming a layer of said second material over said layer of said first material;

forming a layer of a third material over said layer of said second material;

forming a first opening in said layer of said third material to expose said second material, said first opening not extending into substantially any of said layer of said second material;

forming a sidewall spacer of a fourth material on a sidewall surface of said first opening;

removing a first portion of said second material to form a recess in said layer of said second material, said recess does not expose said first material, said recess having a bottom surface consisting essentially of the same material as said first portion of said second material;

removing a second portion of said layer of said second material to form a second opening in said layer of said second material exposing said first material; and

forming a chalcogenide material in said second opening of said second material.

37. The method of claim 36 , further comprising, after said recess is formed, removing at least a portion of said sidewall spacer so as to decrease the thickness of said spacer.

38. The method of claim 36 , further comprising removing at least a portion of said sidewall spacer so as to decrease the thickness of said spacer while removing said second portion of said second material.

39. The method of claim 38 , wherein the rate of removal of said sidewall spacer is greater than the rate of removal of said second portion of said second material.

40. The method of claim 36 , further comprising removing a third portion of said second material from a sidewall surface of said recess while removing said second portion of said second material.

41. The method of claim 38 , further comprising removing a third portion of said second material from a sidewall surface of said recess while removing said second portion of said second material.

Assignments (5)
CHANGE OF NAME Recorded Jul 18, 2016
From: CARLOW INNOVATIONS, LLC
To: OVONYX MEMORY TECHNOLOGY, LLC
Reel/Frame 039379/0077 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2015
From: OVONYX, INC.
To: CARLOW INNOVATIONS LLC
Reel/Frame 037244/0954 →
CONFIRMATORY LICENSE Recorded Mar 16, 2006
From: MISSION RESEARCH SORPORATION, PRIME CONTRACTOR, F2981-D-244/0002; BAE SYSTEMS, SUBCONTRACTOR; OVONYX, INC., SUBCONTRACTOR TO BAE SYSTEMS
To: AIR FORCE, UNITED STATES
Reel/Frame 017779/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2004
From: RODGERS, JOHN C.
To: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION, INC.
Reel/Frame 014252/0140 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2003
From: MAIMON, JON
To: OVONYX, INC.
Reel/Frame 014352/0111 →