Semiconductor package having angulated interconnect surfaces
View Patent ↗Improved electro-mechanical connections between a packaged semiconductor die ( 12 ) and a printed circuit board ( 60 ) with reduced standoff height and pitch are created by the use of a non-planar semiconductor package substrate ( 24 ) having a surface with angulated portions. Electrically conductive surfaces ( 54 ) are formed over the angulated portions. In one embodiment, the electrically conductive surfaces may be formed by forming an electrically conductive surface ( 54 ) over a non-planar or angulated package substrate ( 42 ). The electrically conductive angulated surfaces improve reliability of solder joints ( 70 ) upon connecting the packaged semiconductor die to the printed circuit board ( 60 ). The gaps within the solder mask openings provide a thin profile and improved pitch. In one form, the die may be on a same side of the package as the angulated substrate surface.
1. A semiconductor package comprising:
a package substrate having a first surface and an opposite second surface having a plurality of surface portions that are angulated, the package substrate comprising a plurality of interconnect layers for routing signals;
a semiconductor die positioned on the substrate;
a mask overlying the second surface of the substrate, the mask having a plurality of mask openings; and
an electrically conductive material that overlies each of the plurality of surface portions that are angulated, the electrically conductive material being selectively formed within each of the plurality of mask openings and on a portion of the second surface of the substrate, the electrically conductive material being electrically connected to the semiconductor die via a conductive interconnect through at least a portion of the substrate.
2. The semiconductor package of claim 1 wherein the electrically conductive material further comprises a non-planar conductive surface.
3. The semiconductor package of claim 1 wherein the electrically conductive material further comprises a non-planar conductive material that is elevated more in a central portion of each of the plurality of mask openings than at outlying portions of each of the plurality of mask openings.
4. The semiconductor package of claim 1 wherein the electrically conductive material overlying each of the plurality of surface portions that are angulated is electrically contacted to the semiconductor die from either a central portion or a peripheral portion of the electrically conductive material overlying each of the plurality of surface portions that are angulated.
5. The semiconductor package of claim 1 wherein the electrically conductive material overlies either all or only a portion of each of the plurality of surface portions that are angulated.
6. The semiconductor package of claim 1 wherein the electrically conductive material is one of at least copper, gold, aluminum, nickel, tin, tungsten, lead, silver or palladium.
7. The semiconductor package of claim 1 wherein the electrically conductive material further comprises:
a conductor having a solderable surface, the conductor immediately overlying the second surface of the substrate; and
a reflowed solder material immediately overlying the conductor.
8. The semiconductor package of claim 1 wherein the electrically conductive material further comprises a conductive polymer.
9. The semiconductor package of claim 1 wherein the electrically conductive material further comprises a metal.
10. The semiconductor package of claim 1 wherein the electrically conductive material forms an electrical interconnect.
11. The semiconductor package of claim 1 wherein the semiconductor die is positioned on a same side of the substrate as the plurality of surface portions that are angulated.
12. The semiconductor package of claim 1 further comprising:
a board comprising either a solderable material or a conductive epoxy connected to the electrically conductive material for making electrical contact from the semiconductor die to the board.
13. The semiconductor package of claim 12 wherein the board is in direct physical contact with the mask.
14. The semiconductor package of claim 12 further comprising a gap between the board and the mask to form a standoff height.
15. The semiconductor package of claim 12 wherein the conductive interconnect further comprises conductive vias, traces and means for making electrical contact from the conductive vias to the semiconductor die.
16. The semiconductor package of claim 15 wherein the means for making electrical contact from the conductive vias to the semiconductor die further comprise at least one of wire bonds, conductive epoxy or conductive bumps.
17. The semiconductor package of claim 1 wherein the electrically conductive material is solder and the mask is a solder mask.