Semiconductor alignment aid
View Patent ↗An alignment aid for semiconductor devices. The alignment aid includes an area having a high level of reflectivity and an adjacent area having a of low level of reflectivity. The area having a low level of reflectivity includes at least one layer of tiles located in an interconnect layer of a semiconductor device and located over active circuitry of the semiconductor device. In some examples, the spacings between the tiles in a scan direction of the alignment aid is less than the wavelength of a light (e.g. a laser light) used to scan the alignment aid. In other examples, the width of the tiles in a scan direction of the alignment aid is less than the wave length of a laser used to scan the alignment aid.
1. An alignment aid for a semiconductor device, the alignment aid comprising:
a first area having a first level of reflectivity;
a second area adjacent to the first area and having a second level reflectivity that is less than the first level of reflectivity, wherein the second area includes at least one interconnect layer; and
wherein the at least one layer of tiles is located directly over active circuitry of the semiconductor device.
2. The alignment aid of claim 1 wherein the first area comprises an alignment feature area and the second area comprises a background area.
3. The alignment aid of claim 1 wherein the first area comprises a background area and the second area comprises an alignment feature area.
4. The alignment aid of claim 1 wherein each layer of tiles of the at least one layer of tiles further comprise:
a plurality of dies located in an interconnect layer, each tile of the plurality is spaced apart from an adjacent tile of the plurality in a laser scan direction of the alignment aid by a spacing that is less than a wavelength of a laser light by which the alignment aid is designed to be scanned.
5. The alignment aid of claim 1 wherein each layer of tiles of the at least one layer of tiles further comprise:
a plurality of tiles located in an interconnect layer, each tile of the plurality is spaced apart from an adjacent tile of the plurality in a laser scan direction of the alignment aid by a spacing that is less than 1340 nm.
6. The alignment aid of claim 1 wherein the at least one layer of tiles further comprise:
a plurality of tiles, each tile of the plurality having a width in a laser scan direction of the alignment aid that is less than a wavelength of a laser light by which the alignment aid is designed to be scanned.
7. The alignment aid of claim 1 wherein each layer of the at least one layer of tiles further comprises:
a plurality of tiles, each tile of the plurality is spaced apart from an adjacent tile of the plurality in a laser scan direction of the alignment aid by a spacing that is less than a wavelength of a laser light by which the alignment aid is designed to be scanned.
8. The alignment aid of claim 1 wherein each layer of the at least one layer of tiles further comprises:
a plurality of tiles, each tile of the plurality having a width in a laser scan direction of the alignment aid that is less than a wavelength of a laser light by which the alignment aid is designed to be scanned.
9. The alignment aid of claim 1 wherein each layer of the at laser one layer of tiles further comprises:
a plurality of tiles, each tile of the plurality is spaced apart from an adjacent tile structure of the plurality in a laser scan direction of the alignment aid by a spacing that is less than 1340 nm.
10. The alignment aid of claim 1 wherein the at least one layer of tiles further comprise:
a plurality of tile structures, each tile structure of the plurality having a width in a laser scan direction of the alignment aid that is less than a wavelength of a laser light by which the alignment aid is designed to be scanned.
11. The alignment aid of claim 1 wherein a that layer of tiles of the at least one layer is located in a first interconnect layer and a second layer of tiles of the at least one layer is located in a second interconnect layer, wherein the first layer of tiles and the second layer of tiles are separated by a layer of dielectric material.
12. The alignment aid of claim 1 wherein:
wherein the at least one layer of tiles is located in an interconnect portion;
the interconnect layer portion includes a first number of interconnect layer, wherein each of a second number of layers of the interconnect layer portion includes a layer of tiles of the at least one layer of tiles, wherein the first number is greater than the second number.
13. The alignment aid of claim 12 wherein the second number is two.
14. The alignment aid of claim 1 wherein the active circuitry includes active circuitry in a substrate.
15. The alignment aid of claim 12 wherein the active circuitry includes conductive interconnect structures in an interconnect layer of the interconnect layer portion below the interconnect layers that the at least one layer of tiles are located.
16. The alignment aid of claim 1 wherein the first area includes am alignment feature structure of a reflective material in a top layer of a plurality of interconnect layers.
17. The alignment aid or claim 16 wherein the second area includes a dielectric material in the top layer.
18. The semiconductor device alignment aid of claim 16 wherein the at least one layer of tiles are located in interconnect layers of the plurality of interconnect layers below the top layer.
19. The semiconductor device of claim 1 further comprising:
at least one layer of tiles located below the alignment aid in the first area, each layer of tiles of the at least one layer of tiles in the first area is located in an interconnect layer that a layer of tiles of the at least one layer of tiles in the second area is located.
20. The alignment aid of claim 1 wherein:
the alignment aid includes a first laser scan direction and a second laser scan direction generally orthogonal to the first laser scan direction;
each layer of tiles of the at least one layer tiles further comprises a plurality of tile structures;
each tile structure of the plurality is spaced apart from an adjacent tile structure of the plurality in the first laser scan direction and in the second laser scan direction by a spacing that is less than 1340 nm.
21. The alignment aid of claim 1 wherein the at least one layer of tiles includes a first layer of tiles located in a first interconnect layer and a second layer of tiles located in a second interconnect layer, wherein each tile of the first layer is electrically coupled to a tile of the second layer.
22. A semiconductor device including the alignment aid of claim 1 , the device further comprising:
a substrate, the active circuitry located in the substrate;
an interconnect layer portion including a plurality of interconnect layers located over the substrate, the at least one layer of tiles located in the interconnect portion.