IP Library Granted Patent US 6,909,204
Granted Patent B2
US 6,909,204 · App. 10/404,269 · Granted Jun 21, 2005

System for sequencing a first node voltage and a second node voltage

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Quick Facts
Patent No.
US 6,909,204
App. No.
10/404,269
Granted
Jun 21, 2005
Kind
B2
Abstract

A sequencing system for sequencing a first node voltage at a first node and a second node voltage at a second node which is less than the first node voltage is disclosed. The sequencing system includes a bias circuit configured to provide a bias current in response to the first node voltage beginning to change to a first supply voltage. The sequencing system includes a switch configured to provide a low impedance path between the first node and the second node when the bias circuit is providing the bias current. The switch is configured to provide a high impedance path when the second node voltage is within a range of a second supply voltage which is less than the first supply voltage.

Claims (40)

1. A sequencing system for sequencing a first node voltage at a first node and a second node voltage at a second node which is less than the first node voltage, comprising:

a bias circuit configured to provide a bias current in response to the first node voltage beginning to change to a first supply voltage, wherein the bias circuit includes a voltage reference circuit configured to provide a reference voltage; and

a switch having an input configured to receive the reference voltage, wherein the switch is configured to provide a low impedance path between the first node and the second node when the bias circuit is providing the bias current, wherein the switch is configured to provide a high impedance path when the second node voltage is within a range of a second supply voltage which is less than the first supply voltage, wherein the reference voltage is equal to or less than the second supply voltage, wherein the range is equal to or greater than a difference between the second supply voltage and the reference voltage.

2. The sequencing system of claim 1 , comprising:

at least one power supply coupled to the first node and the second node configured to provide the first supply voltage to the first node and to provide the second supply voltage to the second node.

3. The sequencing system of claim 1 , wherein the first node voltage changes from a ground potential to the first supply voltage and the second node voltage changes from the ground potential to the second supply voltage.

4. The sequencing system of claim 1 , wherein the bias circuit includes:

a conducting circuit configured to conduct the bias current between the first node and the input of the switch.

5. The sequencing system of claim 4 , wherein the switch is a bipolar transistor and the input of the switch is a base of the bipolar transistor, wherein the bipolar transistor has a collector and an emitter coupled to the first and the second nodes.

6. The sequencing system of claim 5 , wherein the range is equal to a sum of a base to emitter voltage drop of the bipolar transistor and a difference between the second supply voltage and the reference voltage.

7. The sequencing system of claim 4 , wherein the conducting circuit is a resistor.

8. The sequencing system of claim 4 , wherein the voltage reference circuit includes one or more diodes coupled in series which are configured to be forward biased when the first node voltage is equal to or greater than a sum of forward bias voltage drops of the diodes, wherein the reference voltage is equal to the sum of the forward bias voltage drops of the diodes.

9. The sequencing system of claim 8 , wherein the diodes are silicon diodes.

10. The sequencing system of claim 9 , wherein the diodes are Schottky barrier diodes.

11. A current routing circuit for conducting current between a first node which has a first node voltage and a second node which has a second node voltage which is less than the first node voltage, comprising:

a current amplifier coupled between the first node and the second node, wherein the current amplifier is configured to conduct current between the first node and the second node when the current amplifier is in a forward active mode and to not conduct current between the first node and the second node when the current amplifier is in a cut-off mode; and

an input circuit coupled to the current amplifier and configured to bias the current amplifier into the forward active mode during a sequencing period in response to the first node voltage beginning to change to a first supply voltage and into the cut-off mode after the sequencing period, wherein the input circuit is configured to provide a reference voltage to the current amplifier, wherein the current amplifier is biased into the cut-off mode when the second node voltage is equal to or greater than the reference voltage, wherein the reference voltage is equal to or less than a second supply voltage at the second node which is less than the first supply voltage.

12. The current routing circuit of claim 11 , wherein the input circuit is configured to provide a bias current to the current amplifier, and wherein the current amplifier is biased in the forward active mode when the second node voltage is less than the reference voltage.

13. The current routing circuit of claim 12 , wherein the first node voltage changes from an initial voltage value to the first supply voltage and the second node voltage changes from the initial voltage value to the second supply voltage, wherein the first node voltage begins changing from the initial voltage value before the second node voltage begins changing from the initial voltage value, wherein before the sequencing period, the first node voltage and the second node voltage are equal to the initial voltage value.

14. The current routing circuit of claim 13 , wherein the initial voltage value is equal to a ground potential.

15. The current routing circuit of claim 11 , wherein a first power supply changes the first node voltage to the first supply voltage and a second power supply changes the second node voltage to the second supply voltage.

16. The current routing circuit of claim 11 , wherein the current amplifier is a bipolar transistor, wherein a base of the bipolar transistor is coupled to the input circuit, and wherein a collector and an emitter of the bipolar transistor are coupled to the first node and the second node.

17. The current routing circuit of claim 11 , wherein the input circuit comprises:

a resistor coupled at a first end to the first node; and

one or more diodes connected in series between a second end of the resistor and a ground potential, wherein the diodes are configured to provide the reference voltage which is equal to a sum of the forward bias voltage drops of the diodes when the first node voltage is equal to or greater than the reference voltage.

18. The current routing circuit of claim 17 , wherein the diodes comprise silicon diodes.

19. The current routing circuit of claim 17 , wherein the diodes comprise Schottky barrier diodes.

20. A sequencing circuit for sequencing a first node voltage at a first node and a second node voltage at a second node which is less than the first node voltage, comprising:

a resistor coupled at a first end to the first node;

one or more diodes connected in series between a second end of the resistor and a ground potential; and

a bipolar transistor having a base coupled to the second end of the resistor, a collector coupled to the first node and an emitter coupled to the second node, wherein the transistor is configured to couple the first node to the second node to pull up the second node voltage to approximately a second supply voltage in response to the first node voltage beginning to change to a first supply voltage, wherein the first supply voltage is greater than the second supply voltage.

21. A method of sequencing a first node voltage at a first node and a second node voltage at a second node which is less than the first node voltage, comprising:

biasing a switch on into a low impedance state by providing a bias current to the switch in response to the first node voltage beginning to change to a first supply voltage;

biasing the switch off into a high impedance state when the second node voltage is within a range of a second supply voltage which is less than the first supply voltage, wherein biasing the switch off includes:

providing a reference voltage to the switch, wherein the reference voltage is equal to or less than the second supply voltage, wherein the range is equal to or greater than a difference between the second supply voltage and the reference voltage.

22. A method of conducting current between a first node which has a first node voltage and a second node which has a second node voltage which is less than the first node voltage, comprising:

biasing a current amplifier into a forward active mode during a sequencing period in response to the first node voltage beginning to change to a first supply voltage to conduct current between the first node and the second node; and

biasing the current amplifier into a cut-off mode after the sequencing period so that no current is conducted between the first node and the second node, wherein biasing the current amplifier into the cut-off mode includes providing a reference voltage to the current amplifier to bias the current amplifier into the cut-off mode when the second node voltage is equal to or greater than the reference voltage, wherein the reference voltage is equal to or less than a second supply voltage at the second node which is less than the first supply voltage.

23. The method of claim 22 , wherein biasing the current amplifier into the forward active mode includes providing a bias current to the current amplifier to bias the current amplifier into the forward active mode when the second node voltage is less than the reference voltage.

24. The method of claim 23 , wherein the first node voltage changes from an initial voltage value to the first supply voltage and the second node voltage changes from the initial voltage value to the second supply voltage, wherein the first node voltage begins changing from the initial voltage value before the second node voltage begins changing from the initial voltage value, wherein before the sequencing period, the first node voltage and the second node voltage are equal to the initial voltage value.

Assignments (12)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 017207 FRAME 0020. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038633/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
RELEASE OF SECURITY INTEREST Recorded May 15, 2013
From: CITICORP NORTH AMERICA, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030420/0048 →
SECURITY AGREEMENT Recorded Feb 24, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: CITICORP NORTH AMERICA, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017207/0020 →