Method and apparatus for automated synthesis of multi-channel circuits
View Patent ↗Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.
1. A method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit; and
automatically transforming the single-channel circuit to generate a second design of a time multiplexed multi-channel circuit wherein the first design of the signal-channel circuit contains at least one negative latency register.
2. The method of claim 1 further comprising:
retiming the time multiplexed multi-channel circuit.
3. The method of claim 2 , wherein the time multiplexed multi-channel circuit is retimed to improve clock frequency.
4. The method of claim 1 further comprising:
identifying a pipeline register set in the time multiplexed multi-channel circuit; and
removing the pipeline register set.
5. The method of claim 1 further comprising:
inserting a pipeline register set in the time multiplexed multi-channel circuit.
6. The method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit; and
automatically transforming the single-channel circuit to generate a second design of a time multiplexed multi-channel circuit, wherein said automatically transforming comprises generating a multi-state Finite-State Machine (FSM) to time multiplex access to logic elements of the first design by multiple channels.
7. The method of claim 6 wherein said transforming further comprises:
generating a multiplexing circuit to time multiplex multiple inputs for the multiple channels onto an input line of the first design.
8. The method of claim 6 wherein said transforming further comprises:
generating a de-multiplexing circuit to time de-multiplex signals from an output line in the first design into multiple outputs for the multiple channels.
9. The method of claim 6 wherein said transforming further comprises:
replacing a channel-specific element in the first design with multiple corresponding elements, each of the multiple corresponding elements being accessed for one of the multiple channels according to a state of the FSM.
10. The method of claim 9 wherein the channel-specific element comprises one of:
a) a constant;
b) a Random Access Memory (RAM) element;
c) a Read Only Memory (ROM) element;
d) a register;
e) a flip-flop; and
f) a negative latency register.
11. The method of claim 9 wherein the channel-specific element is a channel-specific sequential element.
12. The method of claim 11 further comprising:
identifying non-channel-specific sequential elements.
13. The method of claim 12 wherein the non-channel-specific sequential elements comprise a set of pipeline registers.
14. The method of claim 11 wherein the channel-specific sequential element is replaced with a cascade of multiple shifting sequential elements.
15. The method of claim 11 wherein the channel-specific sequential element is replaced with multiple memory elements addressed according to the state of the FSM.
16. The method of claim 11 further comprising:
determining a number of feed-forward cutsets of sequential elements as non-channel-specific sequential elements.
17. The method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit; and
automatically transforming the single-channel circuit to generate a second design of a time multiplexed multi-channel circuit, wherein said automatically transforming comprises replacing a sequential element in the first design with corresponding elements to generate the second design, the corresponding elements being sequentially accessed in the second design according to timing for processing signals from multiple channels.
18. The method of claim 17 wherein the corresponding elements are addressed sequentially.
19. The method of claim 17 wherein the sequential element comprises one of:
a) a constant;
b) a Random Access Memory (RAM) element;
c) a Read Only Memory (ROM) element;
d) a register;
e) a flip-flop; and
f) a negative latency register.
20. The method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit;
generating a conglomerate of single-channel circuits of the first design and information indicating a parallelism in the conglomerate of single-channel circuits; and
applying a folding transformation to the conglomerate of single-channel circuits using the information to generate a second design of time multiplexed multi-channel circuit wherein the first design of the signal-channel circuit contains at least one negative latency register.
21. The method of claim 20 , wherein the information comprises information of a folding set.
22. A machine readable medium containing executable computer program instructions which, when executed by a digital processing system, cause said system to perform a method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit; and
automatically transforming the single-channel circuit to generate a second design of a time multiplexed multi-channel circuit wherein the first design of the signal-channel circuit contains at least one negative latency register.
23. The machine readable medium of claim 22 wherein the method further comprises:
retiming the time multiplexed multi-channel circuit.
24. The machine readale medium of claim 23 , wherein the time multiplexed multi-channel circuit is retimed to improve clock frequency.
25. The machine readable medium of claim 22 wherein the method further comprises:
identifying a pipeline register set in the time multiplexed multi-channel circuit; and
removing the pipeline register set.
26. The machine readable medium of claim 22 wherein the method further comprises:
inserting a pipeline register set in the time multiplexed multi-channel circuit.
27. The machine readable medium containing executable computer program instructions which, when executed by a digital processing system, cause said digital processing system to perform a method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit; and
automatically transforming the single-channel circuit to generate a second design of a time multiplexed multi-channel circuit, wherein said automatically transforming comprises generating a multi-state Finite-State Machine (FSM) to time multiplex access to logic elements of the first design by multiple channels.
28. The machine readable medium of claim 27 wherein said transforming further comprises:
generating a multiplexing circuit to time multiplex multiple inputs for the multiple channels onto an input line of the first design.
29. The machine readable medium of claim 27 wherein said transforming further comprises:
generating a de-multiplexing circuit to time de-multiplex signals from an output line in the first design into multiple outputs for the multiple channels.
30. The machine readable medium of claim 27 wherein said transforming further comprises:
replacing a channel-specific element in the first design with multiple corresponding elements, each of the multiple corresponding elements being accessed for one of the multiple channels according to a state of the FSM.
31. The machine readable medium of claim 30 wherein the channel-specific element comprises one of:
a) a constant;
b) a Random Access Memory (RAM) element;
c) a Read Only Memory (ROM) element;
d) a register;
e) a flip-flop; and
f) a negative latency register.
32. The machine readable medium of claim 30 wherein the channel-specific element is a channel-specific sequential element.
33. The machine readable medium of claim 32 wherein the method further comprises:
identifying non-channel-specific sequential elements.
34. The machine readable medium of claim 33 wherein the non-channel-specific sequential elements comprise a set of pipeline registers.
35. The machine readable medium of claim 32 wherein the channel-specific sequential element is replaced with a cascade of multiple shifting sequential elements.
36. The machine readable medium of claim 32 wherein the channel-specific sequential element is replaced with multiple memory elements addressed according to the state of the FSM.
37. The machine readable medium of claim 32 wherein the method further comprises:
determining a number of feed-forward cutsets of sequential elements as non-channel-specific sequential elements.
38. The machine readable medium containing executable computer program instructions which, when executed by a digital processing system, cause said digital processing system to perform a method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit; and
automatically transforming the single-channel circuit to generate a second design of a time multiplexed multi-channel circuit, wherein said automatically transforming comprises replacing a sequential element in the first design with corresponding elements to generate the second design, the corresponding elements being sequentially accessed in the second design according to timing for processing signals from multiple channels.
39. The machine readable medium of claim 38 wherein the corresponding elements are addressed sequentially.
40. The machine readable medium of claim 38 wherein the sequential element comprises one of:
a) a constant;
b) a Random Access Memory (RAM) element;
c) a Read Only Memory (ROM) element;
d) a register;
e) a flip-flop; and
f) a negative latency register.
41. The machine readable medium containing executable computer program instructions which, when executed by a digital processing system, cause said system to perform a method to design a digital circuit, the method comprising:
receiving a first design of a single-channel circuit;
generating a conglomerate of single-channel circuits of the first design and information indicating a parallelism in the conglomerate of single-channel circuits; and
applying a folding transformation to the conglomerate of single-channel circuits using the information to generate a second design of time multiplexed multi-channel circuit wherein the first design of the signal-channel circuit contains at least one negative latency register.
42. The machine readable medium as in claim 41 , wherein the information comprises information of a folding set.