Architecture for programmable logic device

1. An improved programmable logic device architecture that provides more efficient utilization of resources by enabling access to a defined sequential circuit element in a routing domain associated with a programmable logic block from any other programmable logic block in the device, by incorporating a connecting means in the routing structure operable to selectively connect an input of the defined sequential circuit element in the routing domain to a first signal-pass node of a common interconnect matrix connecting all the programmable logic blocks together via no circuit element other than one or more switch elements and to simultaneously connect an output of the logic circuit element to a second signal-pass node of the common interconnect matrix.

2. An improved programmable logic device architecture as claimed in claim 1 wherein said connecting means is a controlled gate structure that selectively enables the input of the defined sequential circuit element to the interconnect matrix, based on the value of a selection input.

3. An improved programmable logic device architecture as claimed in claim 1 wherein said connecting means provides bi-directional access to the input of the defined sequential circuit element.

4. An improved programmable logic device architecture as claimed in claim 1 wherein the defined sequential circuit element is operable to be coupled to a combinatorial circuit element.

5. A method for improving the utilization of programmable—logic—device resources by enabling access to a defined sequential logic circuit element in the domain of any programmable logic block by selectively connecting an input of the logic circuit element to a first signal-pass node of a common interconnect matrix connecting all the programmable logic blocks together via no circuit element other than one or more pass gates and by simultaneously connecting an output of the logic circuit element to a second signal-pass node of the common interconnect matrix.

6. A method as claimed in claim 5 wherein selective connection is accomplished by connecting a particular input of the logic circuit element to the interconnect matrix, based on the value of a selection input.

7. A method for improving the utilization of programmable-logic-device resources by enabling access to a defined seguential logic circuit element in the domain of any programmable logic block by selectively connecting an input of the logic circuit element to a first signal-pass node of a common interconnect matrix connecting all the programmable logic blocks together via no circuit element other than one or more pass gates and by simultaneously connecting an output of the logic circuit element to a second signal-pass node of the common interconnect matrix, further comprising causing a signal to propagate bi-directionally between the first and second signal-pass nodes.

8. An integrated circuit, comprising:

first and second programmable logic blocks; and

routing resources adjacent to the first programmable logic block and including a sequential logic element having an input and an output, the routing resources operable to couple the input of the sequential logic element to the second logic block via no circuit element other than one or more pass gates and to simultaneously couple the output of the sequential logic element to either the input of one of the programmable logic blocks or to the second logic block.

9. An integrated circuit, comprising:

programmable logic blocks;

routing resources adiacent to one of the programmable logic blocks and including a sequential logic element having an input and an output, the routing resources operable to couple the input of the sequential logic element to one of the logic blocks via no circuit element other than one or more pass gates and to simultaneously couple the output of the sequential logic element to one of the programmable logic blocks;

a tile section;

wherein the routing resources and the adjacent programmable logic block are located within the tile section; and

at least one of the logic blocks coupled to the input and output of the sequential logic element is located outside of the tile section.

10. The integrated circuit of claim 8 wherein the sequential logic element is coupled to a combinatorial logic element.

11. The integrated circuit of claim 8 wherein the routing resources are operable to couple the input and output of the sequential logic element to the same one of the logic blocks.

12. The integrated circuit of claim 8 wherein the sequential logic element comprises a flip-flop.

13. An integrated circuit comprising:

programmable logic blocks; and

routing resources adjacent to one of the programmable logic blocks and including a sequential logic element having an input and an output, the routing resources operable to couple the input of the sequential logic element to one of the logic blocks via no circuit element other than one or more pass gates and to simultaneously couple the output of the sequential logic element to one of the programmable logic blocks;

wherein the routing resources are operable to allow bidirectional communication between the logic block coupled to the input of the sequential logic element and the logic block coupled to the output of the sequential logic element.

14. An integrated circuit comprising:

programmable logic blocks; and

routing resources adjacent to one of the programmable logic blocks and including a sequential logic element having an input and an output, the routing resources operable to couple the input of the sequential logic element to one of the logic blocks via no circuit element other than one or more pass gates and to simultaneously couple the output of the sequential logic element to one of the programmable logic blocks;

wherein the routing resources are operable to allow bidirectional communication via the sequential logic element between the logic block coupled to the input of the sequential logic element and the logic block coupled to the output of the sequential logic element.

15. The integrated circuit of claim 8 wherein the routing resources are operable to couple the input and output of the sequential logic element to different ones of the logic blocks that are not adjacent to the routing resources.

16. An electronic system, comprising:

a first integrated circuit, comprising,

first and second programmable logic blocks, and

routing resources adjacent to the first programmable logic blocks and including a sequential logic element having an input and an output, the routing resources operable to couple the input of the sequential logic element to the second logic blocks via no circuit element other than one or more pass gates and to simultaneously couple the output of the sequential logic element to either the input of one of the programmable logic blocks or to the second logic block.

17. The electronic system of claim 16 , further comprising a second integrated circuit coupled to the first integrated circuit.

18. The electronic system of claim 16 wherein the first integrated circuit comprises a field-programmable gate array.

19. An electronic circuit, comprising:

a circuit node input operable to receive a logic signal;

a flip-flop having an input node and an output node, the input node coupled with the circuit input node via no circuit element other than one or more first switches;

a second switch operable to couple the circuit input node with a distribution node;

a third switch operable to couple the flip-flop output node with the distribution node; and

a plurality of distribution switches, each distribution switch operable to couple the distribution node to a respective distribution output node.

20. The electronic circuit of claim 19 wherein:

the second and third switches each have a respective couple state and a respective decouple state; and

the couple/decouple states of the second switch and the third switch are mutually exclusive.

21. An electronic circuit comprising:

a circuit node input operable to receive a logic signal;

a flip-flop having an input node and an output node, the input node coupled with the circuit input node;

a first switch operable to couple the circuit input node with a distribution node;

a second switch operable to couple the flip-flop output node with the distribution node;

a plurality of distribution switches, each distribution switch operable to couple the distribution node to a respective distribution output node;

a third switch operable to couple the circuit input node to the first switch; and

a fourth switch operable to couple the circuit input node to the second switch.

22. The electronic circuit of claim 21 wherein:

the third and fourth switches each have a respective couple state and a respective decouple state; and

the couple/decouple states of the third switch and the fourth switch are mutually exclusive.

23. A method, comprising:

routing an input node of a sequential logic element disposed within a routing matrix to a first signal-pass node of the routing matrix via no circuit element other than one or more switches, the routing matrix associated with a programmable logic block; and

simultaneously routing an output node of the sequential logic element to a second signal-pass node of the routing matrix.

24. The method of claim 23 wherein the sequential logic element comprises a flip-flop.

25. The integrated circuit of claim 8 wherein the routing resources are operable to respectively couple the input and output of the sequential logic element to different ones of the logic blocks, one of the logic blocks being adjacent to the routing resources.