IP Library Assignment 036940/0693
Patent Assignment
Reel/Frame 036940/0693

Merger

Recorded: 2015-11-02 Pages: 11
Assignor
SICRONIC REMOTE KG, LLC
Executed: 2015-08-11
Assignee
MINERAL LASSEN LLC
2215-B RENAISSANCE DRIVE, SUITE 5, LAS VEGAS, NEVADA, 89119
Covered Properties (45)
System for Rapid Configuration of a Programmable Logic Device
Patent: 6,642,743 →
Application: 10/072,458 →
Publication: US 2002/0114200
Programmable Logic Device Including Bi-Directional Shift Register
Patent: 6,646,465 →
Application: 10/072,461 →
Publication: US 2002/0113618
Concurrent Logic Operations Using Decoder Circuitry of a Look-Up Table
Patent: 6,624,771 →
Application: 10/145,390 →
Publication: US 2002/0175703
Method for Sharing Configuration Data for High Logic Density on Chip
Patent: 7,038,489 →
Application: 10/172,355 →
Publication: US 2002/0194449
System for Simplifying the Programmable Memory to Logic Interface in Fpga
Patent: 6,748,577 →
Application: 10/186,314 →
Publication: US 2003/0005402
Field Programmable Logic Device with Efficient Memory Utilization
Patent: 6,788,104 →
Application: 10/186,346 →
Publication: US 2003/0001614
Decoder Scheme for Making Large Size Decoder
Patent: 6,794,906 →
Application: 10/269,166 →
Publication: US 2004/0070424
Rapid Partial Configuration of Reconfigurable Devices
Patent: 7,206,919 →
Application: 10/319,436 →
Publication: US 2003/0145193
Utilization of Unused Io Block for Core Logic Functions
Patent: 7,157,936 →
Application: 10/347,139 →
Publication: US 2003/0172363
Field Programmable Device
Patent: 6,870,393 →
Application: 10/406,028 →
Publication: US 2004/0017221
Low Power Clock Distribution Scheme
Patent: 6,879,185 →
Application: 10/407,801 →
Publication: US 2003/0218480
Architecture for Programmable Logic Device
Patent: 7,154,299 →
Application: 10/407,802 →
Publication: US 2003/0214321
Hardening Logic Devices
Patent: 6,864,712 →
Application: 10/426,248 →
Publication: US 2004/0212394
Method and Device for Testing Configuration Memory Cells in Programmable Logic Devices (Plds)
Patent: 7,167,404 →
Application: 10/436,895 →
Publication: US 2004/0015758
Plds Providing Reduced Delays in Cascade Chain Circuits
Patent: 6,864,714 →
Application: 10/460,040 →
Publication: US 2003/0234667
Fpga Peripheral Routing with Symmetric Edge Termination at Fpga Boundaries
Patent: 6,888,374 →
Application: 10/464,420 →
Publication: US 2004/0036499
Programmable Logic Devices Having Enhanced Cascade Functions to Provide Increased Flexibility
Patent: 6,873,182 →
Application: 10/608,854 →
Publication: US 2004/0070422
Method and Apparatus of Reloading Erroneous Configuration Data Frames During Configuration of Programmable Logic Devices
Patent: 7,350,134 →
Application: 10/667,199 →
Publication: US 2004/0153923
Mapping of Programmable Logic Devices
Patent: 7,124,392 →
Application: 10/675,908 →
Publication: US 2004/0133869
Sense Amplifier with Feedback-Controlled Bitline Access
Patent: 6,894,541 →
Application: 10/684,076 →
Publication: US 2004/0130353
High Performance Interconnect Architecture for Field Programmable Gate Arrays
Patent: 7,030,648 →
Application: 10/739,395 →
Publication: US 2004/0178821
Programmable Logic Device with Reduced Power Consumption
Patent: 7,078,932 →
Application: 10/830,854 →
Publication: US 2005/0035782
Method and Device for Configuration of Plds
Patent: 7,157,935 →
Application: 10/954,981 →
Publication: US 2005/0127943
Programmable Logic Devices
Patent: 7,606,969 →
Application: 11/005,247 →
Publication: US 2005/0172070
Optimal Mapping of Lut Based Fpga
Patent: 7,415,681 →
Application: 11/025,785 →
Publication: US 2005/0156626
An Improved System for Delay Reduction During Technology Mapping in Fpga
Patent: 7,430,726 →
Application: 11/027,292 →
Publication: US 2005/0177808
Fpga-Based Digital Circuit for Reducing Readback Time
Patent: 7,271,616 →
Application: 11/190,509 →
Publication: US 2006/0022700
Field Programmable Gate Array
Patent: 8,112,466 →
Application: 11/238,123 →
Publication: US 2006/0075012
Configuration Memory Structure
Patent: 7,196,942 →
Application: 11/254,558 →
Publication: US 2006/0120141
Interconnect Structure Enabling Indirect Routing in Programmable Logic
Patent: 7,307,452 →
Application: 11/258,616 →
Publication: US 2006/0139055
Interconnect Structure and Method in Programmable Devices
Patent: 7,750,673 →
Application: 11/261,420 →
Publication: US 2006/0087342
Configurable Logic Device Providing Enhanced Flexibility, Scalability and Providing Area Efficient Implementation of Arithmetic Operation on N-Bit Variables
Patent: 7,372,296 →
Application: 11/263,386 →
Publication: US 2006/0091903
Fpga Having a Direct Routing Structure
Patent: 7,755,387 →
Application: 11/264,674 →
Publication: US 2006/0119388
Rapid Interconnect and Logic Testing of Fpga Device
Patent: 7,477,070 →
Application: 11/294,645 →
Publication: US 2006/0255833
Self Test Structure for Interconnect and Logic Element Testing in Programmable Devices
Patent: 7,779,318 →
Application: 11/318,347 →
Publication: US 2007/0011539
Interconnect Structure Enabling Indirect Routing in Programmable Logic
Patent: 7,414,433 →
Application: 11/952,524 →
Publication: US 2008/0084230
Processing Configuration Data Frames
Patent: 7,774,682 →
Application: 12/032,448 →
Publication: US 2008/0215935
Method for Sharing Configuration Data for High Logic Density on Chip
Patent: 41,561 →
Application: 12/110,205 →
Mapping Programmable Logic Devices
Patent: 8,028,262 →
Application: 12/117,656 →
Publication: US 2008/0209385
Adding or Subtracting Inputs Using a Carry Signal with a Fixed Value of Logic 0
Patent: 7,554,356 →
Application: 12/119,323 →
Publication: US 2008/0252334
Method and Device for Configuration of Plds
Patent: 43,081 →
Application: 12/136,712 →
Interconnect Structure Enabling Indirect Routing in Programmable Logic
Patent: 7,755,388 →
Application: 12/138,281 →
Publication: US 2008/0258764
Technology Mapping for Programmable Logic Devices Using Replicating Logic and Parallel Computations
Patent: 8,024,687 →
Application: 12/188,986 →
Publication: US 2008/0295042
Mapping of Programmable Logic Devices
Patent: 43,378 →
Application: 12/288,359 →
Fpga Having a Direct Routing Structure
Patent: 7,961,004 →
Application: 12/645,236 →
Publication: US 2010/0097099
Related Assignments (8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Feb 2, 2018
From: MINERAL LASSEN LLC
To: INTELLECTUAL VENTURES ASSETS 67 LLC
Reel/Frame 044824/0296 →
Assignment of Assignor's Interest Aug 24, 2018
From: INTELLECTUAL VENTURES ASSETS 67 LLC
To: BICAMERAL LLC
Reel/Frame 046701/0572 →
Assignment of Assignor's Interest Mar 21, 2019
From: INTELLECTUAL VENTURES ASSETS 113 LLC
To: M-RED INC.
Reel/Frame 048661/0804 →
Assignment of Assignor's Interest Mar 22, 2019
From: MINERAL LASSEN LLC
To: INTELLECTUAL VENTURES ASSETS 113 LLC
Reel/Frame 048680/0683 →
Assignment of Assignor's Interest Jan 17, 2020
From: MINERAL LASSEN LLC
To: INTELLECTUAL VENTURES ASSETS 159 LLC
Reel/Frame 051550/0724 →
Nunc Pro Tunc Assignment Mar 23, 2020
From: INTELLECTUAL VENTURES ASSETS 156 LLC
To: INNOVATIVE SILICON SOLUTIONS, LLC
Reel/Frame 052199/0662 →
Corrective Assignment to Correct the Conveying and Receiving Party Previously Recorded at Reel: 052199 Frame: 0662. Assignor(S) Hereby Confirms the Assignment. Mar 28, 2020
From: INTELLECTUAL VENTURES ASSETS 159 LLC
To: INNOVATIVE SILICON SOLUTIONS, LLC
Reel/Frame 052253/0545 →
Change of Name Jan 14, 2021
From: INNOVATIVE SILICON SOLUTIONS LLC
To: HD SILICON SOLUTIONS LLC
Reel/Frame 054993/0795 →