Method and device for configuration of PLDs

1. A Programmable Logic Device providing efficient scalability for configuration memory programming while requiring reduced area for implementation, comprising:

an array of configuration memory cells;

a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells;

a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells;

a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR); and

a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

2. The Programmable Logic Device of claim 1 wherein the Configuration State Machine comprises:

an index register that specifies the number of columns of the configuration array that are to be enabled;

an increment register that contains the number of shifts required in the HSR prior to enabling the column; and

a count address register that provides a count of the number of programmed columns.

3. The Programmable Logic Device of claim 1 wherein the Horizontal Shift Register comprises a plurality of flip-flops connected in series to form a serial shift register with a common clock signal and initialization signal that sets the first flip-flop and clears the remaining flip-flops at the start of the configuration process.

4. A device, comprising:

a configurable memory latch array;

a vertical shift register supplying configuration data to rows of the array; and

a circuit for moving the configuration data from the vertical shift register to one selected column of the array for storage, the circuit comprising:

a horizontal select register operable to select columns within the array;

a horizontal shift register generating control signals driving horizontal select register operation; and

a configuration state machine controlling operation of the horizontal shift register.

5. The device of claim 4 wherein the configuration state machine comprises:

an index register which registers a number of columns to be enabled from a current column specified by the horizontal shift register;

an increment register which registers a number of shifts until selection of a column by the horizontal shift register; and

a count address register which registers a count for each completed operation of moving configuration data from the vertical shift register.

6. The device of claim 4 wherein the configuration state machine comprises:

an index register specifying a number of columns of the array that are to be loaded with configuration data;

an increment register specifying a number of shifts required by the horizontal shift register before enabling a desired column; and

a count address register specifying a count of completed operations to move configuration data from the vertical shift register.

7. A device comprising:

a configurable memory latch array;

a vertical shift register supplying configuration data to rows of the array;

a horizontal shift register; and

a configuration state machine including;

an index register which registers a number of columns to be enabled from a current column specified by the horizontal shift register;

an increment register which registers a number of shifts until selection of a column by the horizontal shift register; and

a count address register which registers a count for each completed operation of moving configuration data from the vertical shift register.

8. A device comprising:

a configurable memory latch array;

a vertical shift register supplying configuration data to rows of the array;

a horizontal shift register; and

a configuration state machine including:

an index register specifying a number of columns of the array that are to be loaded with configuration data;

an increment register specifying a number of shifts required by the horizontal shift register before enabling a desired column; and

a count address register specifying a count of completed operations to move configuration data from the vertical shift register.