Patent Assignment
Reel/Frame 020385/0574
Assignment of Assignor's Interest
Recorded: 2008-01-17
Received: 2008-01-17
Pages: 7
Assignor
STMICROELECTRONICS PVT, LTD.
Executed: 2007-11-12
Assignee
STMICROELECTRONICS NV
39 CHEMIN DU CHAMP-DE-FILLES, 1228 PALN-LES-QUATES, GENEVA, CHX, SWITZERLAND
Covered Properties
(44)
Efficient Method for Mapping a Logic Design on Field Programmable Gate Arrays
Application:
11/319,015 →
Self Test Structure for Interconnect and Logic Element Testing in Programmable Devices
Application:
11/318,347 →
Rapid Interconnect and Logic Testing of Fpga Device
Application:
11/294,645 →
Fpga Having a Direct Routing Structure
Application:
11/264,674 →
Configurable Logic Device Providing Enhanced Flexibility, Scalability and Providing Area Efficient Implementation of Arithmetic Operation on N-Bit Variables
Application:
11/263,386 →
Interconnect Structure and Method in Programmable Devices
Application:
11/261,420 →
Interconnect Structure Enabling Indirect Routing in Programmable Logic
Application:
11/258,616 →
Configuration Memory Structure
Application:
11/254,558 →
Field Programmable Gate Array
Application:
11/238,123 →
Fpga-Based Digital Circuit for Reducing Readback Time
Application:
11/190,509 →
An Improved System for Delay Reduction During Technology Mapping in Fpga
Application:
11/027,292 →
Optimal Mapping of Lut Based Fpga
Application:
11/025,785 →
Programmable Logic Devices
Application:
11/005,247 →
Method and Device for Configuration of Plds
Application:
10/954,981 →
Method for Mapping a Logic Circuit to a Programmable Look Up Table (Lut)
Application:
10/830,862 →
Programmable Logic Device with Reduced Power Consumption
Application:
10/830,854 →
High Performance Interconnect Architecture for Field Programmable Gate Arrays
Application:
10/739,395 →
Sense Amplifier with Feedback-Controlled Bitline Access
Application:
10/684,076 →
Mapping of Programmable Logic Devices
Application:
10/675,908 →
Method and Apparatus of Reloading Erroneous Configuration Data Frames During Configuration of Programmable Logic Devices
Application:
10/667,199 →
Programmable Logic Devices Having Enhanced Cascade Functions to Provide Increased Flexibility
Application:
10/608,854 →
Fpga Peripheral Routing with Symmetric Edge Termination at Fpga Boundaries
Application:
10/464,420 →
Plds Providing Reduced Delays in Cascade Chain Circuits
Application:
10/460,040 →
Method and Device for Testing Configuration Memory Cells in Programmable Logic Devices (Plds)
Application:
10/436,895 →
Architecture for Programmable Logic Device
Application:
10/407,802 →
Low Power Clock Distribution Scheme
Application:
10/407,801 →
Utilization of Unused Io Block for Core Logic Functions
Application:
10/347,139 →
Rapid Partial Configuration of Reconfigurable Devices
Application:
10/319,436 →
Candy Brush and Confectionery Container Set
Application:
29/170,527 →
Combined Candy Brush and Container Therefor
Application:
29/170,521 →
Candy Brush for a Confectionery Product
Application:
29/170,526 →
Decoder Scheme for Making Large Size Decoder
Application:
10/269,166 →
Ice Cream Cone-Shaped Candy
Application:
29/168,584 →
Field Programmable Logic Device with Efficient Memory Utilization
Application:
10/186,346 →
Method for Sharing Configuration Data for High Logic Density on Chip
Application:
10/172,355 →
Concurrent Logic Operations Using Decoder Circuitry of a Look-Up Table
Application:
10/145,390 →
Programmable Logic Device Including Bi-Directional Shift Register
Application:
10/072,461 →
System for Rapid Configuration of a Programmable Logic Device
Application:
10/072,458 →
Self Sealing Cap with Spring and Post
Application:
10/072,269 →
Confectionery with Body, Handle and Container
Application:
09/874,446 →
Alien Head for Confectionery Product
Application:
29/142,932 →
Alien Head for Confectionery Product
Application:
29/142,928 →
Alien Head for Confectionery Product
Application:
29/142,929 →
Alien Body for Confectionery Product
Application:
29/142,921 →