Method and device for testing configuration memory cells in programmable logic devices (PLDS)
View Patent ↗A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.
1. A programmable logic device (PLD) comprising:
a configuration memory array comprising a plurality of memory cells and a plurality of data lines connected therebetween;
a selector for selecting a group of said memory cells;
an input data storage device connected to said data lines for storing input data for the selected group of said memory cells;
an output data storage device connected to said data lines; and
configuration logic for controlling said selector, said input data storage device, and said output data storage device so that the input data is stored in said output data storage device for testing said data lines and without altering data stored in said memory cells.
2. The PLD of claim 1 wherein the input data comprises at least one of configuration data to be stored in the selected group of said memory cells, and test data for testing the selected group of said memory cells.
3. The PLD of claim 1 wherein said memory cells are arranged in rows and columns, and wherein the groups of said memory cells comprise at least one of rows and columns of said memory cells.
4. The PLD of claim 1 wherein said selector comprises: a serial-in parallel-out shift register for providing enabling signals to enable the selected group of said memory cells.
5. The PLD of claim 1 wherein said input data storage device comprises a serial-in parallel-out shift register.
6. The PLD of claim 1 wherein said output data storage device comprises a parallel-in serial-out shift register.
7. The PLD of claim 1 wherein said configuration logic causes said selector to deselect all of said memory cells during storage of the input data in the output data storage device.
8. The PLD of claim 1 wherein the PLD is implemented as a programmable gate array.
9. A method for testing a configuration memory array of a programmable logic device (PLD), the configuration memory array comprising a plurality of memory cells and a plurality of data lines connected therebetween, the method comprising:
storing input data in an input data storage device connected to the data lines; and
controlling the input data storage device and an output data storage device also connected to the data lines so that the input data is stored in the output data storage device for testing the data lines and without altering data stored in the memory cells.
10. The method of claim 9 wherein controlling further comprises deselecting all of the memory cells during storage of the input data in the output data storage device.
11. The method of claim 9 wherein the input data comprises at least one of configuration data and test data.
12. The method of claim 9 wherein the memory cells are arranged in rows and columns, and wherein the groups of the memory cells comprise at least one of rows and columns of the memory cells.
13. The method of claim 9 wherein the input data storage device comprises a serial-in parallel-out shift register.
14. The method of claim 9 wherein the output data storage device comprises a parallel-in serial-out shift register.