FPGA peripheral routing with symmetric edge termination at FPGA boundaries

1. A Field Programmable Gate Array (FPGA) providing symmetrical routing across its entire area including a periphery, comprising:

peripheral routing lines of equal length that are symmetrically deflected orthogonally; and

switch boxes and connection boxes positioned at the periphery and connected to the peripheral routing lines, for maintaining constant routing channel width.

2. A Field Programmable Gate Array (FPGA) as claimed in claim 1 , further comprising a plurality of programmable logic blocks (PLB), wherein the peripheral routing lines are quad lines that span four PLB sides.

3. A Field Programmable Gate Array (FPGA) as claimed in claim 1 , further comprising a plurality of channels, wherein deflected routing lines from adjacent channels are merged and have the equal length.

4. A Field Programmable Gate Array (FPGA) as claimed in claim 1 wherein the connection boxes are positioned between the peripheral switch boxes.

5. A method for providing symmetrical routing across an entire area, including a periphery, of an FPGA, comprising the steps of:

symmetrically deflecting peripheral routing lines of equal length orthogonally; and

connecting switch boxes and connection boxes at the periphery, for maintaining constant routing channel width.

6. The method of claim 5 wherein the peripheral routing lines are quad lines that span four PLB sides.

7. The method of claim 5 , further including merging deflected routing lines from adjacent channels in a manner that retains the equal length of the lines.

8. The method of claim 5 wherein the connection boxes are positioned between the peripheral switch boxes.

9. A field programmable gate array, comprising:

an array of programmable logic boxes;

a plurality of switch boxes positioned outside of the array and in a peripheral channel; and

a plurality of peripheral routing lines positioned in the peripheral channel and connected to the switch boxes, each of the switch boxes being connected to respective first and second routing lines, of the plurality of routing lines, that symmetrically extend in opposite directions from each other.

10. The field programmable gate array of claim 9 wherein each of the routing lines of the plurality are of equal length.

11. The field programmable gate array of claim 9 wherein the first and second routing lines both extend in a first direction from a side of one of the switch boxes, the first routing line being deflected in a second direction transverse to the first direction, and the second routing line being deflected in a third direction transverse to the first direction and opposite to the second direction.

12. The field programmable gate array of claim 9 wherein the peripheral routing lines are quad lines that span four sides of the programmable logic blocks.

13. The field programmable gate array of claim 9 , wherein the array of programmable logic blocks include a plurality of core channels extending between groups of the programmable logic blocks, the field programmable gate array further comprising a core routing line that extends from a first one of the core channels into the peripheral channel and into a second one of the core channels.

14. The field programmable gate array of claim 9 wherein the core routing line and the peripheral routing lines have equal lengths.

15. The field programmable gate array of claim 9 , further comprising connection boxes positioned between the switch boxes and connected to the routing lines.