FPGA-based digital circuit for reducing readback time

1. A digital circuit in an FPGA for reducing readback time comprising:

a shift register having a plurality of latches, a clock and a reset signal being provided to said latches;

an interconnect circuit between each pair of latches of said shift register for providing a selective data frame from the desired latch/latches; and

a control signal generator coupled to a plurality of independent control inputs of said interconnect circuit to enable read back of said selected frames in reduced time.

2. The digital circuit of claim 1 wherein said interconnect circuit comprises a 1×2 switch matrix, a 2×1 switch matrix or a 2×2 switch matrix.

3. The digital circuit of claim 2 wherein the 1×2 switch matrix is coupled between a first two of the plurality of latches, the 2×1 switch matrix is coupled between a last two of the plurality of latches, and the 2×2 switch matrix is coupled between the remaining latches of said shift register.

4. The digital circuit of claim 2 wherein the 1×2 switch matrix comprises a demultiplexer.

5. The digital circuit of claim 2 wherein the 2×1 switch matrix comprises a multiplexer.

6. A method for reducing read back time in FPGA comprising:

inputting data to a first latch of a shift register;

applying clock and reset signals to plurality of latches of the shift register;

outputting data from the first latch to an interconnect circuit and subsequent interconnect circuits between each pair of said latches of the shift register;

selecting the desired latch or latches through the interconnect circuits individually enabled by a control signal generator for selection of a particular data frame or frames; and

outputting a selected data frame for read back in reduced time.

7. A digital circuit in an FPGA comprising:

a shift register including a plurality of latches, each latch including a data input, a data output, a clock input, and a reset input, wherein the clock inputs are coupled together for receiving a clock input signal, and the reset inputs are coupled together for receiving a reset signal; and

an interconnect circuit including a plurality of switches for coupling the data output of an Nth latch in the plurality of latches to an (N+1)th latch in the plurality of latches, or for individually bypassing the plurality of latches.

8. The digital circuit of claim 7 wherein a first of said plurality of switches comprises a 1×2 switch.

9. The digital circuit of claim 7 wherein a last of said plurality of switches comprises a 2×1 switch.

10. The digital circuit of claim 7 wherein said plurality of switches comprises a plurality of 2×2 switches.

11. The digital circuit of claim 7 further comprising:

an upper line for coupling an upper switch output of an Nth switch to an upper switch input of an (N+1)th switch.

12. The digital circuit of claim 7 further comprising: a bottom line for coupling a bottom switch output of an Nth switch to a bottom switch input of an (N+1)th switch.

13. The digital circuit of claim 7 , wherein at least one of the plurality of switches comprises first and second selection control inputs.

14. A digital circuit in an FPGA for reducing read back time comprising:

a shift register having a plurality of latches, a clock and a reset signal being provided to said latches;

an interconnect circuit between each pair of latches of said shift register for providing a selective data frame from the desired latch/latches, said interconnect circuit comprising a 1×2 switch matrix coupled between a first two of the plurality of latches, a 2×1 switch matrix coupled between a last two of the plurality of latches, or a 2×2 switch matrix coupled between the remaining latches of said shift register; and

a control signal generator coupled to a control input of said interconnect circuit to enable read back of said selected frames in reduced time.

15. A digital circuit in an FPGA for reducing readback time comprising:

a shift register having a plurality of latches, a clock and a reset signal being provided to said latches;

an interconnect circuit between each pair of latches of said shift register for providing a selective data frame from the desired latch/latches, said interconnect circuit comprising a 1×2 switch matrix comprising a demultiplexer, a 2×1 switch matrix, or a 2×2 switch matrix; and

a control signal generator coupled to a control input of said interconnect circuit to enable read back of said selected frames in reduced time.

16. A digital circuit in an FPGA comprising:

a shift register including a plurality of latches, each latch including a data input, a data output, a clock input, and a reset input, wherein the clock inputs are coupled together for receiving a clock input signal, and the reset inputs are coupled together for receiving a reset signal; and

an interconnect circuit including a plurality of switches for coupling the data output of an Nth latch in the plurality of latches to an (N+1)th latch in the plurality of latches, or for selectively bypassing at least one of the plurality of latches, wherein said plurality of switches comprises a plurality of 2×2 switches.

17. A digital circuit in an FPGA comprising:

a shift register including a plurality of latches, each latch including a data input, a data output, a clock input, and a reset input, wherein the clock inputs are coupled together for receiving a clock input signal, and the reset inputs are coupled together for receiving a reset signal;

an interconnect circuit including a plurality of switches for coupling the data output of an Nth latch in the plurality of latches to an (N+1)th latch in the plurality of latches, or for selectively bypassing at least one of the plurality of latches; and

an upper line for coupling an upper switch output of an Nth switch to an upper switch input of an (N+1)th switch.

18. A digital circuit in an FPGA comprising:

a shift register including a plurality of latches, each latch including a data input, a data output, a clock in put, and a reset input, wherein the clock inputs are coupled together for receiving a clock input signal, and the reset inputs are coupled together for receiving a reset signal;

an interconnect circuit including a plurality of switches for coupling the data output of an Nth latch in the plurality of latches to an (N+1)th latch in the plurality of latches, or for selectively bypassing at least one of the plurality of latches; and

a bottom line for coupling a bottom switch output of an Nth switch to a bottom switch input of an (N+1)th switch.

19. A digital circuit in an FPGA comprising:

a shift register including a plurality of latches, each latch including a data input, a data output, a clock input, and a reset input, wherein the clock inputs are coupled together for receiving a clock input signal, and the reset inputs are coupled together for receiving a reset signal; and

an interconnect circuit including a plurality of switches for coupling the data output of an Nth latch in the plurality of latches to an (N+1)th latch in the plurality of latches, or for selectively bypassing at least one of the plurality of latches, wherein at least one of the plurality of switches comprises first and second selection control inputs.