IP Library › Granted Patent US 7,147,766
Granted Patent B2
US 7,147,766 · App. 10/407,892 · Granted Dec 12, 2006

Chip interconnect and packaging deposition methods and structures

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Quick Facts
Patent No.
US 7,147,766
App. No.
10/407,892
Granted
Dec 12, 2006
Kind
B2
Abstract

The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

Claims (38)

1. A method of electroplating a metal in a feature formed in a substrate, the substrate having a top surface, the feature having a bottom and sidewalls, the method comprising:

depositing a barrier layer on the top surface of the substrate and the bottom and sidewalls of the feature;

depositing a seed layer of the metal on the barrier layer;

removing the seed layer from the top surface of the substrate, thereby exposing the barrier layer on the top surface of the substrate and leaving the seed layer on the sidewalls and on the bottom of the feature;

during the removing, applying an electrical potential between the substrate and an electrode; and

electroplating the metal on the seed layer so that the metal fills the feature with substantially no electroplating on the top surface.

2. A method of electroplating a metal according to claim 1 , wherein the removing comprises chemical mechanical polishing.

3. A method of electroplating a metal according to claim 2 , wherein the metal comprises copper.

4. A method of electroplating a metal according to claim 3 , wherein the barrier layer comprises tantalum and tantalum nitride.

5. A method of electroplating a metal according to claim 1 , wherein the metal comprises copper.

6. A method of electroplating a metal according to claim 5 , wherein the barrier layer comprises tantalum and tantalum nitride.

7. A method of electroplating a metal according to claim 1 , wherein the barrier layer comprises tantalum and tantalum nitride.

8. A method of electroplating a metal according to claim 1 , wherein the electroplating the metal fills the feature to an excess, the method further comprising removing the excess metal so that a top surface of the metal is substantially planar with the barrier layer on the top surface of the substrate.

9. A method of electroplating a metal according to claim 1 , further comprising removing the barrier layer from the top surface of the substrate.

10. A method of electroplating a metal according to claim 1 , wherein the electrode comprises an anode and the substrate comprises a cathode.

11. A method of electroplating a metal according to claim 1 , wherein the electrode comprises a cathode and the substrate comprises an anode.

12. A method of electroplating a metal according to claim 1 , wherein the electrode comprises a cathode and the seed layer on the top surface of the substrate comprises an anode.

13. A method of electroplating a metal according to claim 1 , wherein removing the seed layer comprises polishing the seed layer on the top surface of the substrate with a pad.

14. A method of electroplating a metal according to claim 1 , wherein electroplating the metal comprises polishing the top surface of the substrate with a pad.

15. A method of electroplating a metal according to claim 1 , wherein the removing the seed layer and the electroplating the metal occur simultaneously.

16. A method of electroplating a metal on a substrate including a feature having a bottom and sidewalls, the substrate having a barrier layer and a seed layer deposited on a top surface of the substrate and on the bottom and the sidewalls of the feature, the method comprising:

removing the seed layer from the top surface of the substrate, thereby exposing the barrier layer on the top surface of the substrate and leaving the seed layer on the sidewalls and on the bottom of the feature;

during the removing, applying an electrical potential between the substrate and an electrode; and

electroplating the metal on the seed layer so that the metal fills the feature, with substantially no electroplating on the top surface.

17. A method of electroplating a metal according to claim 16 , wherein the removing comprises chemical mechanical polishing.

18. A method of electroplating a metal according to claim 17 , wherein the metal comprises copper.

19. A method of electroplating a metal according to claim 18 , wherein the barrier layer comprises tantalum and tantalum nitride.

20. A method of electroplating a metal according to claim 16 , wherein the metal comprises copper.

21. A method of electroplating a metal according to claim 20 , wherein the barrier layer comprises tantalum and tantalum nitride.

22. A method of electroplating a metal according to claim 16 , wherein the barrier layer comprises tantalum and tantalum nitride.

23. A method of electroplating a metal according to claim 16 , wherein the electroplating the metal fills the feature to an excess, the method further comprising removing the excess metal so that a top surface of the metal is substantially planar with the barrier layer on the top surface of the substrate.

24. A method of electroplating a metal according to claim 16 , further comprising removing the barrier layer from the top surface of the substrate.

25. A method of electroplating a metal according to claim 16 , wherein the electrode comprises an anode and the substrate comprises a cathode.

26. A method of electroplating a metal according to claim 16 , wherein the electrode comprises a cathode and the substrate comprises an anode.

27. A method of electroplating a metal according to claim 16 , wherein the electrode comprises a cathode and the seed layer on the top surface of the substrate comprises an anode.

28. A method of electroplating a metal according to claim 16 , wherein removing the seed layer comprises polishing the seed layer on the top surface of the substrate with a pad.

29. A method of electroplating a metal according to claim 16 , wherein electroplating the metal comprises polishing the top surface of the substrate with a pad.

30. A method of electroplating a metal according to claim 16 , wherein the removing the seed layer and the electroplating the metal occur simultaneously.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2007
From: ASM NUTOOL, INC.
To: NOVELLUS SYSTEMS, INC.
Reel/Frame 019000/0080 →
CHANGE OF NAME Recorded Jul 1, 2005
From: NUTOOL, INC.
To: ASM NUTOOL, INC.
Reel/Frame 016733/0702 →