Multiplier-based processor-in-memory architectures for image and graphics processing
A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits smaller than those in the input data (e.g., 4×4 adders if the input data are 8-bit numbers). The ALU implements various arithmetic algorithms for addition, multiplication, and other operations. A secondary processing logic includes adders in series and parallel to permit vector operations as well as operations on longer scalars. A self-repairing ALU is also disclosed.
1. A computational random access memory comprising:
a memory comprising N columns, N being an integer; and
an arithmetic logic unit, in communication with the N columns in the memory, the arithmetic logic unit comprising:
M multipliers, M being an integer divisible into N, each of the M multipliers being configured to multiply two N/M-bit numbers; and
an adder stage, in communication with the M multipliers to receive outputs of the M multipliers, for forming and outputting calculation results in accordance with the outputs of the M multipliers,
wherein the arithmetic logic unit is configured to multiply two N-bit numbers by:
(a) multiplying, in the M multipliers, a plurality of combinations of N/M bits of the two N-bit numbers to form a plurality of partial products; and
(b) accumulating, in the adder stage, the plurality of partial products to provide a product of the two N-bit numbers,
wherein the arithmetic logic unit is configured to add two N-bit numbers by multiplication by one in the multipliers and forming a sum in the adder stage.
2. A computational random access memory comprising:
a memory comprising N columns, N being an integer; and
an arithmetic logic unit, in communication with the N columns in the memory, the arithmetic logic unit comprising:
M multipliers, M being an integer divisible into N, each of the M multipliers being configured to multiply two N/M-bit numbers; and
an adder stage, in communication with the M multipliers to receive outputs of the M multipliers, for forming and outputting calculation results in accordance with the outputs of the M multipliers; wherein:
the memory comprises a plurality of groups of N columns;
a plurality of said arithmetic logic units are provided, one for each of the plurality of groups of N columns; and
the computational random access memory further comprises a secondary processing logic, in communication with the plurality of arithmetic logic units to receive outputs of the plurality of arithmetic logic units, the secondary processing logic comprising a plurality of adders for combining calculation results from the plurality of arithmetic logic units to permit calculations on numbers of more than N bits.
3. The computational random access memory of claim 2 , wherein the plurality of groups of N columns of the memory are arranged in a plurality of rows, each of the plurality of rows comprising said arithmetic logic units and said secondary processing logic.
4. The computational random access memory of claim 3 , wherein, in each of the rows, the groups of columns are interconnected by a diagonal connection.
5. The computational random access memory of claim 3 , wherein, in each of the rows, the groups of columns are interconnected by an N-bit word connection.
6. The computational random access memory of claim 5 , wherein, in each of the rows, the groups of columns are also interconnected to a diagonal connection.
7. The computational random access memory of claim 6 , further comprising a plurality of two-way shift registers, each interconnecting two of the groups of N columns in two of the rows.
8. A computational random access memory comprising:
a memory comprising N columns, N being an integer; and
an arithmetic logic unit, in communication with the N columns in the memory, the arithmetic logic unit comprising:
M multipliers, M being an integer divisible into N, each of the M multipliers being configured to multiply two N/M-bit numbers; and
an adder stage, in communication with the M multipliers to receive outputs of the M multipliers, for forming and outputting calculation results in accordance with the outputs of the M multipliers; wherein:
the arithmetic logic unit further comprises a repair multiplier in addition to the M multipliers; and
each of the M multipliers comprises an input for receiving a repair signal which controls that multiplier to replace its output with an output received from the repair multiplier.
9. The computational random access memory of claim 8 , wherein the arithmetic logic unit further comprises a repair-input muxing unit for selecting inputs to the repair multiplier.