Integrated circuit with DMA module for loading portions of code to a code memory for execution by a host processor that controls a video decoder
View Patent ↗A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.
1. An integrated circuit for decoding video data, said integrated circuit comprising:
a video decoder for decompressing the video data;
a code memory for storing a portion of a program and a particular instruction, said portion of the program indicating a location of another portion of the program, said program for controlling the video decoder;
a host processor for controlling the video decoder and for executing the portion of the program, and the particular instruction after the portion of the program; and
a direct memory access module for loading the code memory with the another portion of the program from the location;
wherein execution of the instruction by the processor causes the processor to transmit a signal to the direct memory access module, said signal causing the direct memory module to load the code memory with the another portion of the program and transmit another signal to the processor after loading the code memory with the another portion, and cessation of program execution by the processor until the processor receives the another signal from the direct memory access module.
2. The integrated circuit of claim 1 , said integrated circuit further comprising:
a display engine for preparing the decompressed video data for display; and
wherein the host processor controls the display engine and wherein the program is also for controlling the display engine.