Method and system for data encryption and decryption
View Patent ↗An aspect of the of the invention may include the transfer of a block of data from a first memory location to a second memory location in a DRAM. During the transfer of the block of data from the first memory location, if an encryption mode is selected, the data may be buffered, encrypted, and then stored in the second memory location. If a decryption mode is selected, the transferred data may be buffered, decrypted and then stored in the second memory location. If a bypass mode is selected, the data may be buffered and then stored in the second memory location. In this regard, the encryption/decryption operations may be bypassed.
1. A method for encrypting and decrypting data, the method comprising:
receiving data from a memory device coupled to a first memory interface;
determining which one of an encryption operation, a decryption operation and a bypass operation to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip;
transferring said received data back to said memory device; and
buffering said received data in at least one buffer integrated within said chip prior to said execution of said encryption and decryption operations.
2. The method according to claim 1 , comprising identifying at least one encryption key to be utilized for said execution of said encryption operation.
3. The method according to claim 2 , comprising identifying at least one decryption key to be utilized for said execution of said decryption operation.
4. The method according to claim 3 , comprising:
instructing an encryption/decryption processor to perform said execution of said encryption operation using said at least one encryption key if said determined operation is an encryption operation; and
instructing an encryption/decryption processor to perform said execution of said decryption operation using said at least one decryption key if said determined operation is a decryption operation.
5. The method according to claim 4 , comprising bypassing said encryption and decryption operations of said encryption/decryption processor if said bypass operation is to be performed.
6. A machine-readable storage having stored thereon, a computer program having at least one code section for encrypting and decrypting data, the at least one code section executable by a machine for causing the machine to perform steps comprising:
receiving data from a memory device coupled to a first memory interface;
determining which one of an encryption operation, a decryption operation and a bypass operation to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip; and
transferring said received data back to said memory device; and
buffering said received data in at least one buffer integrated within said chip prior to said execution of said encryption and decryption operations.
7. The machine-readable storage according to claim 6 , comprising code for identifying at least one encryption key to be utilized for said execution of said encryption operation.
8. The machine-readable storage according to claim 7 , comprising code for identifying at least one decryption key to be utilized for said execution of said decryption operation.
9. The machine-readable storage according to claim 8 , comprising code for instructing an encryption/decryption processor to perform said execution of said encryption operation using said at least one encryption key if said determined operation is an encryption operation and for instructing an encryption/decryption processor to perform said execution of said decryption operation using said at least one decryption key if said determined operation is a decryption operation.
10. The machine-readable storage according to claim 9 , comprising code for bypassing said encryption and decryption operations of said encryption/decryption processor if said bypass operation is to be performed.
11. A system for encrypting and decrypting data, the system comprising:
at least one buffer enables receiving of data from a memory device coupled to a first memory interface;
at least one key and encryption/decryption selector and controller enables determining of one of: an encryption, decryption and bypass operations, to be performed on said received data;
at least one encryption/decryption processor enables execution of one of: said encryption and decryption operations, on said received data within a chip: and
said at least one encryption/decryption processor enables transfer of one of: a resulting data from said encryption and decryption operations, and data from said bypass operation, back to said memory device; and
said at least one buffer enables buffering of said received data prior to said execution of said encryption and decryption operations.
12. The system according to claim 11 , wherein said key and encryption/decryption selector and controller enables identification of at least one encryption key to be utilized for said execution of said encryption operation.
13. The system according to claim 12 , wherein said key and encryption/decryption selector and controller enables identification of at least one decryption key to be utilized for said execution of said decryption operation.
14. The system according to claim 13 , wherein said key and encryption/decryption selector and controller enables instructing of an encryption/decryption processor to perform said execution of said encryption operation using said at least one encryption key if said determined operation is an encryption operation and to instruct said encryption/decryption processor to perform said execution of said decryption operation using said at least one decryption key if said determined operation is a decryption operation.
15. The system according to claim 14 , comprising at least one selector enables selection of a bypass of said encryption and decryption operations of said encryption/decryption processor if said bypass operation is to be performed.
16. The system according to claim 11 , comprising a CPU interface enables control of said chip via an external processor through the CPU interface.
17. A method for encrypting and decrypting data, the method comprising:
receiving data from a memory device coupled to a first memory interface;
determining which one of: an encryption operation, a decryption operation, and a bypass operation, is to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip; and
transferring said received data back to said memory device; and
buffering said received data in at least one buffer integrated within said chip prior to said execution of said encryption and decryption operations; and
buffering said resulting data from said encryption and decryption operations, and said data from said bypass operation in said at least one buffer prior to said transfer back to said memory device.
18. A method for encrypting and decrypting data, the method comprising:
receiving data from a memory device coupled to a first memory interface;
determining which one of an encryption operation, a decryption operation and a bypass operation to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip; and
transferring said received data back to said memory device; and
said receiving comprises receiving said data from a first location of said memory device and said transferring comprises transferring said resulting data and said bypass data to a second memory location of said memory device.
19. A method for encrypting and decrypting data, the method comprising:
receiving data from a memory device coupled to a first memory interface;
determining which one of an encryption operation, a decryption operation and a bypass operation to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip; and
transferring said received data back to said memory device, wherein said memory device is external to said chip.
20. A machine-readable storage having stored thereon, a computer program having at least one code section for encrypting and decrypting data, the at least one code section executable by a machine for causing the machine to perform steps comprising:
receiving data from a memory device coupled to a first memory interface;
determining which one of an encryption operation, a decryption operation and a bypass operation to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip; and
transferring said received data back to said memory device;
buffering said received data in at least one buffer integrated within said chip prior to said execution of said encryption and decryption operations; and
buffering said resulting data from said encryption and decryption operations, and said data from said bypass operation in said at least one buffer prior to said transfer back to said memory device.
21. A machine-readable storage having stored thereon, a computer program having at least one code section for encrypting and decrypting data, the at least one code section executable by a machine for causing the machine to perform steps comprising:
receiving data from a memory device coupled to a first memory interface;
determining which one of an encryption operation, a decryption operation and a bypass operation to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip; and
transferring said received data back to said memory device; and
receiving said data from a first location of said memory device and said transferring comprises transferring said resulting data and said bypass data to a second memory location of said memory device.
22. A machine-readable storage having stored thereon, a computer program having at least one code section for encrypting and decrypting data, the at least one code section executable by a machine for causing the machine to perform steps comprising;
receiving data from a memory device coupled to a first memory interface;
determining which one of an encryption operation, a decryption operation and a bypass operation to be performed within a chip on said received data;
if said determined encryption operation is to be performed,
executing said encryption operation on said received data within said chip; and
transferring resulting data from said executed encryption operation back to said memory device;
if said determined decryption operation is to be performed,
executing said decryption operation on said received data within said chip; and
transferring resulting data from said executed decryption operation back to said memory device;
if said determined bypass operation is to be performed,
executing said bypass operation on said received data within said chip; and
transferring said received data back to said memory device, wherein said memory device is external to said chip.
23. A system for encrypting and decrypting data, the system comprising:
at least one buffer that enables receiving of data from a memory device coupled to a first memory interface;
at least one key and encryption/decryption selector and controller that enables determining of one of: an encryption, decryption and bypass operations, to be performed on said received data;
at least one encryption decryption processor that enables execution of one of: said encryption and decryption operations, on said received data within a chip;
said at least one encryption/decryption processor enables transfer of one of: a resulting data from said encryption and decryption operations, and data from said bypass operation, back to said memory device, wherein said at least one buffer buffers said received data in said at least one buffer integrated within said chip prior to said execution of said encryption and decryption operations; and
said at least one buffer buffers said resulting data from said encryption and decryption operations, and buffers said data from said bypass operation prior to said transfer back to said memory device.
24. A system for encrypting and decrypting data, the system comprising:
at least one buffer that enables receiving of data from a memory device coupled to a first memory interface;
at least one key and encryption/decryption selector and controller that enables determining of one of: an encryption, decryption and bypass operations, to be performed on said received data;
at least one encryption/decryption processor that enables execution of one of: said encryption and decryption operations, on said received data within a chip; and
said at least one encryption/decryption processor enables transfer of one of: a resulting data from said encryption and decryption operations, and data from said bypass operation, back to said memory device, wherein said at least one buffer buffers said received data in said at least one buffer integrated within said chip prior to said execution of said encryption and decryption operations; and
a memory interface that receives said received data from a first location of said memory device and transfers said resulting data and said bypass data to a second memory location of said memory device.
25. The system according to claim 24 wherein said memory interface is integrated within said chip.
26. A system for encrypting and decrypting data, the system comprising:
at least one buffer that enables receiving of data from a memory device coupled to a first memory interface;
at least one key and encryption/decryption selector and controller that enables determining of one of: an encryption, decryption and bypass operations, to be performed on said received data;
at least one encryption/decryption processor that enables execution of one of: said encryption and decryption operations, on said received data within a chip; and
said at least one encryption/decryption processor enables transfer of one of: a resulting data from said encryption and decryption operations, and data from said bypass operation back to said memory device, wherein said at least one buffer buffers said received data in said at least one buffer integrated within said chip prior to said execution of said encryption and decryption operations: wherein said memory device is external to said chip.