Method of updating a shift register
There is disclosed a method of updating a pseudo noise code shift retiser in a noise code shift register in a software implemented CDMA system from a current value, including representing a tap polynomial as a tap polynomial binary sequence logically AND-ing the value of a last stage of the current value of the register with each of the bits of the tap polynomial sequence and logically XOR-ing the result of the logical AND operation with the current value of the register.
1. A method of updating a pseudo noise code shift register of a software-implemented radio telecommunication system from a current value to a new value, including:
a) representing a tap polynomial as a tap polynomial binary sequence;
b) logically AND-ing the value of a last stage of the current value of the register with each of the bits of the tap polynomial sequence;
c) logically XOR-ing the result of step b) with the current value of the register; and
d) updating the pseudo noise code shift register according to step c), wherein
representing the tap polynomial involves producing a binary sequence which is shifted by one bit towards the most significant bit, with the least significant bit set to 1, and the method involves shifting the current value of the register by one bit towards the most significant bit before performing step (b).
2. A method as claimed in claim 1 , wherein step (b) is performed by extending said value of a last stage of said register to at least a sequence length of said tap polynomial binary sequence and logically AND-ing said sign extended value with said tap polynomial binary sequence.
3. A method as claimed in claim 1 , wherein the method involves the steps of shifting the current value of the register one bit towards the most significant bit and assigning the value of the last stage of the current value of the register to the first stage of the new value of the register after step (c).
4. A method as claimed in claim 1 , wherein the sequence length is 42-bits.
5. A method as claimed in claim 1 , wherein the sequence length is 15-bits.
6. A method as claimed in claim 1 , wherein a computer processor is used to carry out step (a), step (b), step (c) and step (d).
7. A method as claimed in claim 6 , wherein said processor is a digital signal processor.
8. A computer program for updating a pseudo noise code shift register of a software-implemented radio telecommunication system from a current value to a new value, the computer program recorded on a computer-readable medium and comprising:
a) code for representing a tap polynomial as a tap polynomial binary sequence;
b) code for logically AND-ing the value of a last stage of the current value of the register with each of the bits of the tap polynomial sequence to form an intermediate value;
c) code for logically XOR-ing the intermediate value with the current value of the register; and
d) updating the pseudo code shift register according to step c) wherein representing the tap polynomial involves producing a binary sequence which is shifted by one bit towards the most significant bit, with the least significant bit set to 1, whereby the current value of the register is shifted by one bit towards the most significant bit before logically AND-ing the value of the last stage of said register with each of the bits of said tap polynomial sequence to form said intermediate value.
9. The computer program of claim 8 , wherein said value of a last stage of said register is extended to at least a sequence length of said tap polynomial binary sequence.