Method and apparatus for accelerated post-silicon testing and random number generation
View Patent ↗A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.
1. A method of providing accelerated post-silicon testing for a silicon hardware, comprising:
computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint;
performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint;
manufacturing the silicon hardware using the instrumented logic design;
computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware;
comparing the simulation cumulative record of state to the silicon cumulative record of state; and
outputting a result of comparing the simulation cumulative record of state to the silicon cumulative record of state, wherein outputting comprises displaying a message based on the result,
wherein computing the simulation cumulative record of state uses a first output value and a second output value of a simulation state element.
2. The method of claim 1 , further comprising:
generating a random number using the silicon cumulative record of state.
3. The method of claim 2 , further comprising:
providing the random number to a computer program executing on a computer device.
4. The method of claim 1 , further comprising:
transferring the set of test instructions, the cycle breakpoint, and the simulation cumulative record of state to a storage area accessible to the silicon hardware; and
generating the instrumented logic design by instrumenting a logic design.
5. The method of claim 4 , wherein the cycle breakpoint is used to determine when computing the silicon cumulative record of state is performed.
6. The method of claim 1 , wherein computing the simulation cumulative record of state comprises:
computing a checksum using an output value of a state element of the simulation.
7. The method of claim 1 , wherein computing the silicon cumulative record of state comprises:
computing a checksum using an output value of a state element of the silicon hardware.
8. The method of claim 1 , wherein the simulation cumulative record of state is a subset of a total state of the simulation.
9. The method of claim 1 , wherein the silicon cumulative record of state is a subset of a total state of the silicon hardware.
10. The method of claim 1 , wherein the simulation cumulative record of state is computed in association with a predetermined cycle breakpoint of a plurality of cycles of the simulation.
11. The method of claim 10 , wherein the simulation is executed on a cycle-accurate simulator.
12. A system for providing accelerated post-silicon testing for a silicon hardware, comprising:
a simulator configured to generate a simulation state value by performing a simulation of an instrumented logic design using a plurality of test instructions and a cycle breakpoint;
a checksum unit configured to compute a simulation cumulative record of state using the simulation state value;
a silicon hardware configured to generate a silicon cumulative record of state using the set of test instructions and the cycle breakpoint; and
a silicon checksum unit configured to compute a silicon cumulative record of state using the silicon cumulative record of state,
wherein computing the silicon cumulative record of state uses a first output value and a second output value of a state element of the silicon hardware.
13. The system of claim 12 , further comprising:
a comparator configured to compare a value of the silicon cumulative record of state and a value of the simulation cumulative record of state;
a logic design and instrumentation instructions used to generate the instrumented logic design.
14. The system of claim 12 , wherein the silicon hardware is manufactured using the instrumented logic design.
15. The system of claim 12 , wherein the cycle breakpoint is used to determine when the silicon cumulative record of state is computed.
16. The system of claim 12 , further comprising:
a random number generator configured to use the silicon cumulative record of state to generate a random number.
17. A computer system providing accelerated post-silicon testing for a silicon hardware, comprising:
a processor;
a memory;
a storage device; and
software instructions stored in the memory for enabling the computer system to perform:
computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint;
performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint;
manufacturing the silicon hardware using the instrumented logic design;
computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and
comparing the simulation cumulative record of state to the silicon cumulative record of state,
wherein computing the simulation cumulative record of state uses a first output value and a second output value of a simulation state element.
18. The computer system of claim 17 , further comprising software instructions to perform:
generating a random number using the silicon cumulative record of state.
19. The computer system of claim 17 , further comprising software instructions to perform:
transferring the set of test instructions, the cycle breakpoint, and the simulation cumulative record of state to a storage area accessible to the silicon hardware;
generating the instrumented logic design by instrumenting a logic design; and
outputting the result of comparing the simulation cumulative record of state to the silicon cumulative record of state.
20. An apparatus for providing accelerated post-silicon testing of a silicon hardware, comprising:
means for computing a simulation cumulative record of state of a first value of a state element by performing a simulation of an instrumented logic design using a set of test instructions;
means for manufacturing the silicon hardware using the instrumented logic design;
means for generating a second value of the state element by executing the set of test instructions using the silicon hardware;
means for computing a silicon cumulative record of state using the second value of the state element; and
means for comparing the simulation cumulative record of state to the silicon cumulative record of state,
wherein computing the simulation cumulative record of state uses a first output value and a second output value of a simulation state element.