Semiconductor device with a capacitor having upper and lower shield layers
View Patent ↗The semiconductor device comprises a semiconductor substrate 10 ; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34 , a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14; 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22; 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.
1. A semiconductor device comprising:
a semiconductor substrate;
a capacitor element formed above the semiconductor substrate and including a lower electrode, a capacitor insulation film formed on the lower electrode and an upper electrode formed on the capacitor insulation film;
a lower shield layer formed below the capacitor element;
an upper shield layer formed above the capacitor element;
a lower electrode lead-out interconnection layer formed between the capacitor element and the lower shield layer and electrically connected to the lower electrode; and
an upper electrode lead-out interconnection layer formed between the capacitor element and the upper shield layer and electrically connected to the upper electrode,
a plurality of holes being formed in each of the lower shield layer, the upper shield layer, the lower electrode lead-out interconnection layer and the upper electrode lead-out interconnection layer,
an area of parts of the lower shield layer and the lower electrode lead-out interconnection layer, which are opposed to each other, and an area of parts of the upper shield layer and the upper electrode lead-out interconnection layer, which are opposed to each other being respectively set so that a parasitic capacity between the lower shield layer and the lower electrode lead-out interconnection layer and a parasitic capacity between the upper shield layer and the upper electrode lead-out interconnection layer being substantially equal to each other.
2. A semiconductor device according to claim 1 , wherein
a gap between the lower shield layer and the lower electrode lead-out interconnection layer and a gap between the upper shield layer and the upper electrode lead-out interconnection layer are different from each other.
3. A semiconductor device according to claim 1 , wherein
a dielectric constant of a first insulation film formed between the lower shield layer and the lower lead-out interconnection layer and a dielectric constant of a second insulation film formed between the upper shield layer and the upper lead-out interconnection layer are different from each other.