Integrated circuit memory devices having memory cells therein that utilize phase-change materials to support non-volatile data retention
An integrated circuit memory device includes a semiconductor substrate and a first electrically insulating layer that extends on the semiconductor substrate and has a first contact hole extending therethrough. An electrically conductive plug is provided in the first contact hole. A phase-change material layer pattern is provided as a non-volatile storage medium. The phase-change material layer pattern has a bottom surface that is electrically connected to the electrically conductive plug. A second electrically insulating layer is provided on the phase-change material layer pattern. The second electrically insulating layer has a second contact hole therein. This contact hole exposes a portion of an upper surface of the phase-change material layer pattern. To improve data writing efficiency, the area of the exposed portion of the upper surface of the phase-change material layer pattern is less than a maximum cross-sectional area of the electrically conductive plug. A plate electrode is also provided. This plate electrode is electrically connected to the phase-change material layer pattern. Barrier layers may also be provided directly on the plug and directly on the exposed portion of the upper surface.
1. An integrated circuit memory cell, comprising:
a first electrically conductive barrier layer;
a phase-change material layer pattern extending on and contacting an upper surface of said first electrically conductive barrier layer;
an electrically insulating layer extending on said phase-change material layer pattern and having a contact hole therein; and
an electrically conductive non-phase-change material region extending through the contact hole and contacting less than an entire upper surface of said phase-change material layer pattern.
2. The memory cell of claim 1 , wherein said phase-change material layer pattern comprises a chalcogenide alloy.
3. The memory cell of claim 2 , wherein the chalcogenide alloy is a GeSbTe alloy.
4. The memory cell of claim 1 , wherein said first electrically conductive barrier layer comprises a first metal nitride barrier layer; and wherein said electrically conductive non-phase-change material region comprises a second metal nitride barrier layer.
5. The memory cell of claim 1 , further comprising an insulating spacer that extends between said electrically conductive non-phase-change material region and a sidewall of the contact hole.
6. An integrated circuit memory cell, comprising:
a semiconductor substrate;
a first electrically insulating layer that extends on said semiconductor substrate and has a first contact hole extending therethrough;
an electrically conductive plug that extends in the first contact hole;
a phase-change material layer pattern having a bottom surface that is electrically connected to said electrically conductive plug;
a second electrically insulating layer that extends on said phase-change material layer pattern, said second electrically insulating layer having a second contact hole therein that exposes a reduced portion of an upper surface of said phase-change material layer pattern having an area that is less than a maximum cross-sectional area of said electrically conductive plug; and
a non-phase-change material layer that extends through the second contact hole and contacts the reduced portion of the upper surface of said phase-change material layer pattern so that an area of contact between the upper surface of said phase-change material layer and said non-phase-change material layer is less than the maximum cross-sectional area of said electrically conductive plug.
7. The memory cell of claim 6 , further comprising:
a first barrier layer pattern disposed between said electrically conductive plug and said phase-change material layer pattern.
8. The memory cell of claim 7 , further comprising an insulating spacer that extends between said non-phase-change material layer and a sidewall of the second contact hole.
9. The memory cell of claim 6 , wherein said phase-change material layer pattern comprises a chalcogenide alloy.
10. The memory cell of claim 7 , wherein said first barrier layer pattern and said non-phase-change material layer comprise metal nitride.
11. An integrated circuit memory cell, comprising:
a semiconductor substrate;
a first electrically insulating layer that extends on said semiconductor substrate and has a first contact hole extending therethrough;
an electrically conductive plug that extends in the first contact hole;
a first barrier layer pattern extending on and contacting said electrically conductive plug;
a phase-change material layer pattern extending on and contacting said first barrier layer pattern;
an oxidation resistant layer pattern extending on contacting an upper surface of said phase-change material layer pattern;
a second electrically insulating layer that extends on said oxidation resistant layer pattern, said second electrically insulating layer and said oxidation resistant layer pattern having a second contact hole that extends therethrough and exposes a reduced portion of an upper surface of said phase-change material layer pattern;
a second barrier layer that extends into the second contact hole and contacts the reduced portion of the upper surface of said phase-change material layer pattern so that an area of contact between said second barrier layer and the reduced portion of the upper surface of said phase-change material layer pattern is less than a maximum cross-sectional area of said electrically conductive plug;
a plate electrode on said second barrier layer; and
an access transistor that extends in said semiconductor substrate and has a source region that is electrically connected to said electrically conductive plug.
12. The memory cell of claim 11 , further comprising an insulating spacer that extends between said second barrier layer and a sidewall of the second contact hole.
13. The memory cell of claim 11 , wherein said phase-change material layer pattern comprises a chalcogenide alloy.
14. The memory cell of claim 11 , wherein said oxidation resistant layer pattern comprises a material selected from the group consisting of SiN, BN, SiC and ZnS.