IP Library Granted Patent US 7,523,465
Granted Patent B2
US 7,523,465 · App. 10/422,528 · Granted Apr 21, 2009

Methods and apparatus for generating speculative helper thread spawn-target points

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Quick Facts
Patent No.
US 7,523,465
App. No.
10/422,528
Granted
Apr 21, 2009
Kind
B2
Abstract

Methods and an apparatus for generating a speculative helper thread for cache prefetch are disclosed. The disclosed techniques select spawn-target pairs based on profile data and a series of calculations. Helper threads are then generated to launch at the selected spawn points in order to prefetch software instructions (or data) for a single-threaded software application. The generated helper threads are then attached to the single-threaded software application to create a multi-threaded software application.

Claims (45)

1. A method of generating a speculative helper thread, the method comprising:

identifying a code region in main thread software instructions based on cache misses;

selecting a spawn-target pair, the spawn-target pair including a target point preceding the code region and a spawn point preceding the target point, the spawn-target pair selection being based on a spawn-target selection calculation, comprising calculating a posteriori probability associated with the spawn-target pair;

generating helper thread software instructions to launch a helper thread at the spawn point to prefetch a subset of the main thread software instructions, wherein the spawn-target selection calculation is indicative of the benefit of the helper thread; and

attaching the helper thread software instructions to the main thread software instructions.

2. A method as defined in claim 1 , wherein calculating the posteriori probability associated with the spawn-target pair comprises determining a plurality of path probabilities.

3. A method as defined in claim 1 , wherein the spawn-target selection calculation further comprises calculating an expected path length between the spawn point and the target point.

4. A method as defined in claim 1 , wherein the spawn-target selection calculation further comprises calculating a path length variance between the spawn point and the target point.

5. A method as defined in claim 1 , wherein the spawn-target selection calculation further comprises calculating a prefetch slack associated with the spawn-target pair.

6. A method as defined in claim 5 , wherein calculating the prefetch slack comprises determining a difference in execution cycles between a prefetch of an instruction by the helper thread and an attempted fetch of the instruction by the main thread.

7. A method as defined in claim 6 , wherein the spawn-target selection calculation further comprises calculating an expected path length between the spawn point and the target point.

8. A method as defined in claim 7 , wherein the spawn-target selection calculation comprises calculating a path length variance between the spawn point and the target point.

9. A method as defined in claim 1 , wherein spawn-target selection calculation further comprises calculating an expected path footprint.

10. A method as defined in claim 9 , wherein calculating the expected path footprint comprises calculating an average amount of memory required to store a plurality of instructions along a path defined by two instructions in the main thread.

11. A method as defined in claim 1 , further comprising calculating a reaching probability associated with the spawn-target pair.

12. A method as defined in claim 11 , wherein calculating the reaching probability comprises determining a product of a plurality of path probabilities.

13. A method as defined in claim 1 , wherein identifying a code region in main thread software instructions comprises reading profile information associated with the main thread software instructions.

14. A method as defined in claim 13 , wherein reading profile information associated with the main thread software instructions comprises reading profile information associated with the main thread software instructions to identify a code region in the main thread software instructions that incurs performance loss due to instruction-cache misses.

15. A method as defined in claim 1 , wherein the spawn-target selection calculation is based on a path expression mapping.

16. A method as defined in claim 1 , wherein selecting a spawn-target pair comprises unselecting one or more other spawn-target pairs.

17. A machine readable medium storing instructions structured to cause a machine to:

identify a code region in the main thread software instructions based on cache misses;

select a spawn-target pair, the spawn-target pair including a target point preceding the code region and a spawn point preceding the target point, the spawn-target pair selection being based on a spawn-target selection calculation, comprising calculating a posteriori probability associated with the spawn-target pair;

generate helper thread software instructions to launch a helper thread at the spawn point to prefetch a subset of the main thread software instructions; and

attach the helper thread software instructions to the main thread software instructions.

18. A machine readable medium as defined in claim 17 , wherein the instructions are structured to cause the machine to calculate an expected path length between the spawn point and the target point.

19. A machine readable medium as defined in claim 17 , wherein the instructions are structured to cause the machine to calculate a path length variance between the spawn point and the target point.

20. A machine readable medium as defined in claim 17 , wherein the instructions are structured to cause the machine to calculate a prefetch slack associated with the spawn-target pair.

21. A machine readable medium as defined in claim 17 , wherein the instructions are structured to cause the machine to calculate an expected path footprint.

22. A machine readable medium as defined in claim 17 , wherein the instructions are structured to compile the main thread.

23. A machine readable medium as defined in claim 22 , wherein the subset of the main thread software instructions prefetched by the helper thread are structured to be executed by spare hardware resources on a simultaneous multi-threading (SMT) processor.

24. A machine readable medium as defined in claim 17 , wherein the spawn-target selection calculation is based on a path expression mapping.

25. A computer comprising:

a processor;

a memory operatively coupled to the processor, the memory storing a software tool and an application program, the software tool causing the computer to:

identify a code region in the application program based on cache misses;

select a spawn-target pair in the application program, the spawn-target pair including a target point preceding the code region and a spawn point preceding the target point, the spawn-target pair selection being based on a spawn-target selection calculation, comprising calculating a posteriori probability associated with the spawn-target pair;

generate helper thread instructions to launch a helper thread at the spawn point to prefetch a subset of the application program; and

attach the helper thread instructions to the application program.

26. A computer as defined in claim 25 , wherein the software tool causes the computer to calculate an expected path length between the spawn point and the target point.

27. A computer as defined in claim 25 , wherein the software tool causes the computer to calculate a path length variance between the spawn point and the target point.

28. A computer as defined in claim 25 , wherein the software tool causes the computer to calculate a prefetch slack associated with the spawn-target pair.

29. A computer as defined in claim 25 , wherein the software tool causes the computer to calculate an expected path footprint.

30. A computer as defined in claim 25 , wherein the processor comprises a simultaneous multi-threading (SMT) processor.

31. A computer as defined in claim 25 , wherein the spawn-target selection calculation is based on a path expression mapping.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061827/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2003
From: AAMODT, TOR M.; WANG, HONG; SHEN, JOHN; HAMMARLUND, PER
To: INTEL CORPORATION
Reel/Frame 014377/0789 →