Patent Assignment
Reel/Frame 061827/0686
Assignment of Assignor's Interest
Recorded: 2022-11-01
Pages: 161
Assignor
INTEL CORPORATION
Executed: 2022-07-18
Assignee
TAHOE RESEARCH, LTD.
BLANCHARDSTOWN CORPORATE PARK 2, PLAZA 255, SUITE 2A, DUBLIN, D15 YH6H, IRELAND
Covered Properties
(605)
Digital Still Camera System and Complementary-Color-Filtered Array Interpolation Method
Low power subsystem for portable computers
Application:
09/752,644 →
Publication:
US 2002/0086719
Self-Timed Sneak Current Cancellation
Context Pipelines
Presentation Server
System and Method for Dynamic Link Aggregation in a Shared I/O Subsystem
System and Method for Span Port Configuration
System and Method for Implementing Logical Switches in a Network System
Clock Signal Circuitry for Multi-Protocol High-Speed Serial Interface Circuitry
Patent:
7,180,972 →
Application:
10/273,899 →
Pld Debugging Hub
Self-Timed Voltage-Subtraction Sneak Current Cancellation Method and Apparatus
Methods and apparatus for generating navigation information on the fly
Application:
10/335,112 →
Publication:
US 2003/0095790
Logic Circuitry with Shared Lookup Table
Patent:
6,798,240 →
Application:
10/351,026 →
Control-quasi-independent-points guided speculative multithreading
Application:
10/356,435 →
Publication:
US 2004/0154010
Method and Apparatus for a User to Interface with a Mobile Computing Device
Methods and Apparatus for Generating Speculative Helper Thread Spawn-Target Points
Interface for a Programmable Logic Device
Patent:
6,894,531 →
Application:
10/444,741 →
Programmable Logic Device Serial Interface Having Dual-Use Phase-Locked Loop Circuitry
Patent:
6,867,616 →
Application:
10/455,773 →
Communication ports in a data driven architecture
Application:
10/600,048 →
Publication:
US 2004/0257372
Selectable Dynamic Reconfiguration of Programmable Embedded Ip
Patent:
6,842,034 →
Application:
10/612,253 →
Low Warpage Flip Chip Package Solution-Channel Heat Spreader
Patent:
6,888,238 →
Application:
10/616,858 →
Method for Operating a Pll Frequency Synthesis Circuit
Embedded Microprocessor for Integrated Circuit Testing and Debugging
Patent:
7,539,900 →
Application:
10/629,508 →
Electrically-Programmable Integrated Circuit Antifuses
Patent:
6,897,543 →
Application:
10/646,013 →
Functional Pre-Configuration of a Programmable Logic Device
Patent:
7,030,646 →
Application:
10/654,518 →
Adjustable Differential Input and Output Drivers
Patent:
6,864,704 →
Application:
10/669,298 →
Dynamically-Adjustable Differential Output Drivers
Patent:
6,943,588 →
Application:
10/670,146 →
Apparatus and Methods for Shared Memory Interfaces in Programmable Logic Devices
Patent:
6,828,822 →
Application:
10/678,798 →
Programmable Phase-Locked Loop Circuitry for Programmable Logic Device
Method and Circuit Configuration for Mixing a Digital Signal with an Analogue Signal
Providing services to an open platform implementing subscriber identity module (SIM) capabilities
Application:
10/718,369 →
Publication:
US 2005/0108534
Preventative congestion control for application support
Application:
10/728,676 →
Publication:
US 2005/0122904
Method and Apparatus for Buffering Streaming Media
Programmable Logic Resource with Data Transfer Synchronization
Patent:
7,003,423 →
Application:
10/741,593 →
Methods and Apparatus to Manage System Power and Performance
Switching Device Utilizing Requests Indicating Cumulative Amount of Data
Method to support XML-based security and key management services in a pre-boot execution environment
Application:
10/746,919 →
Publication:
US 2005/0149729
Cmos Device with Metal and Silicide Gate Electrodes and a Method for Making It
Integrated Stacked Microchannel Heat Exchanger and Heat Spreader
Programmable Logic Device with on-Chip Nonvolatile User Memory
Patent:
7,190,190 →
Application:
10/754,432 →
Method for Secure Key Exchange
Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Method and architecture for secure transmission of data within optical switched networks
Application:
10/774,813 →
Publication:
US 2005/0175183
Adaptive Compression and Decompression of Bandlimited Signals
Patent:
7,009,533 →
Application:
10/778,880 →
Enhanced Data Converters Using Compression and Decompression
Patent:
7,088,276 →
Application:
10/778,881 →
Multiplier-Accumulator Block Mode Splitting
Saturation and Rounding in Multiply-Accumulate Blocks
System and Method to Support Platform Firmware as a Trusted Process
Parallelizing mark-sweep-compact garbage collections
Application:
10/793,707 →
Publication:
US 2005/0198088
Programmable Logic Device Having Nonvolatile Memory with User Selectable Power Consumption
Patent:
6,853,603 →
Application:
10/797,493 →
Highly Configurable Pll Architecture for Programmable Logic
Integrated Circuits with Temperature-Change and Threshold-Voltage Drift Compensation
Patent:
6,933,869 →
Application:
10/802,590 →
Method and architecture for security key generation and distribution within optical switched networks
Application:
10/804,487 →
Publication:
US 2005/0177749
Switching device based on aggregation of packets
Application:
10/804,674 →
Publication:
US 2005/0207436
System and Method for Combining User and Platform Authentication in Negotiated Channel Security Protocols
Shared cryptographic key in networks with an embedded agent
Application:
10/809,315 →
Publication:
US 2005/0213768
Apparatus for Adjusting a Clock Frequency of a Variable Speed Bus
Omnibus Logic Element Including Look Up Table Based Logic Elements
Patent:
7,167,022 →
Application:
10/810,117 →
Bit Slip Circuitry for Serial Data Signals
Patent:
7,440,532 →
Application:
10/830,277 →
Configurable Clock Network for Programmable Logic Device
Patent:
7,075,365 →
Application:
10/830,562 →
Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Apparatus and Methods for Multi-Gate Silicon-on-Insulator Transistors
Patent:
7,112,997 →
Application:
10/849,074 →
Generating Optimized and Secure Ip Cores
Patent:
7,165,229 →
Application:
10/852,832 →
Techniques for Reducing Power Consumption in Memory Cells
Patent:
6,972,987 →
Application:
10/856,187 →
Memory Interface Phase-Shift Circuitry to Support Multiple Frequency Ranges
Patent:
7,126,399 →
Application:
10/857,221 →
Multiple Data Rate Memory Interface Architecture
Patent:
7,176,714 →
Application:
10/857,396 →
Debuggable Opaque Ip
Patent:
7,409,652 →
Application:
10/861,893 →
Apparatus and Methods for Adjusting Performance of Integrated Circuits
Deposition apparatus for providing uniform low-k dielectric
Application:
10/881,095 →
Publication:
US 2005/0284371
Vpa Logic Circuits
Patent:
7,193,432 →
Application:
10/882,579 →
Configurable Circuits, Ic's, and Systems
Patent:
7,157,933 →
Application:
10/882,583 →
Configurable Logic Circuits with Commutative Properties
Patent:
7,126,373 →
Application:
10/882,839 →
Configurable Circuits, Ic's, and Systems
Patent:
7,193,440 →
Application:
10/882,946 →
Non-Sequentially Configurable Ic
Patent:
7,167,025 →
Application:
10/883,051 →
Vpa Interconnect Circuit
Patent:
7,126,381 →
Application:
10/883,213 →
Configurable Circuits, Ic's, and Systems
Patent:
7,109,752 →
Application:
10/883,276 →
Configurable Circuits, Ic's, and Systems
Logic Circuitry with Shared Lookup Table
Selective Download of Corridor Map Data
Integrated Circuit Employable with a Power Converter
Integrated Circuit Incorporating Higher Voltage Devices and Low Voltage Devices Therein
Integrated Circuit Employable with a Power Converter
Method of Forming an Integrated Circuit Employable with a Power Converter
Method of Forming an Integrated Circuit Incorporating Higher Voltage Devices and Low Voltage Devices Therein
Method of Forming an Integrated Circuit Incorporating Higher Voltage Devices and Low Voltage Devices Therein
Cache filtering using core indicators
Application:
10/936,952 →
Publication:
US 2006/0053258
Programmable Low-Voltage Differential Signaling Output Driver
Patent:
7,236,018 →
Application:
10/937,518 →
Placement of Map Labels
Adaptive Power Supply Voltage Regulation for Programmable Logic
Patent:
7,142,009 →
Application:
10/942,692 →
Next Generation 8B10B Architecture
Selectable Dynamic Reconfiguration of Programmable Embedded Ip
Patent:
7,071,726 →
Application:
11/005,390 →
Apparatus and methods for adjusting performance characteristics of programmable logic devices
Application:
11/006,420 →
Publication:
US 2006/0119382
Circuit Arrangement Provided with a Phase-Locked Loop and Transmitter-Receiver with Said Circuit Arrangement
Providing Access to Data Shared by Packet Processing Threads
Adjustable Differential Input and Output Drivers
Patent:
6,972,588 →
Application:
11/029,275 →
High-Performance Memory Interface Circuit Architecture
Patent:
7,227,395 →
Application:
11/055,125 →
Selectable Inversion of Differential Input and/or Output Pins in Programmable Logic Devices
Patent:
7,242,221 →
Application:
11/056,442 →
Method and System for Using Boundary Scan in a Programmable Logic Device
Patent:
7,248,070 →
Application:
11/059,929 →
Electrically-Programmable Integrated Circuit Antifuses
Patent:
7,272,067 →
Application:
11/060,925 →
Method and Apparatus for Accessing Contents of Memory Cells
Patent:
7,230,869 →
Application:
11/081,870 →
Method and Apparatus for Reduced Power Cell
Patent:
7,272,031 →
Application:
11/081,874 →
Semiconductor device with a high-k gate dielectric and a metal gate electrode
Application:
11/089,247 →
Publication:
US 2006/0220090
Trusted platform module apparatus, systems, and methods
Application:
11/094,840 →
Publication:
US 2006/0230439
Self-Timed Sneak Current Cancellation
Modular Processor Debug Core Connection for Programmable Chip Systems
Patent:
7,627,784 →
Application:
11/101,027 →
Low Warpage Flip Chip Package Solution-Channel Heat Spreader
Interface for a Programmable Logic Device
Patent:
7,245,147 →
Application:
11/119,375 →
Programmable Phase-Locked Loop Circuitry for Programmable Logic Device
Dynamically-Adjustable Differential Output Drivers
Patent:
7,397,270 →
Application:
11/138,919 →
Method and System for Improving Memory Interface Data Integrity in Plds
Patent:
7,102,544 →
Application:
11/142,732 →
Charge Pump with Reduced Current Mismatch
Patent:
7,385,429 →
Application:
11/142,880 →
Phase Locked Loop with a Modulator
Adjustable Differential Input and Output Drivers
Patent:
7,245,144 →
Application:
11/169,242 →
Dynamic Frequency Divider with Improved Leakage Tolerance
Patent:
7,453,294 →
Application:
11/169,955 →
Method and Apparatus for Providing Software-Based Security Coprocessors
Methods and Apparatus for Generating Endorsement Credentials for Software-Based Security Coprocessors
Fabrication of Channel Wraparound Gate Structure for Field-Effect Transistor
Volatile Memory Elements with Elevated Power Supply Levels for Programmable Logic Device Integrated Circuits
Configurable Clock Network for Programmable Logic Device
Patent:
7,286,007 →
Application:
11/282,876 →
Programmable Logic Device with Differential Communications Support
Patent:
7,505,331 →
Application:
11/286,165 →
Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Ball Grid Array Package-to-Board Interconnect Co-Design Apparatus
Patent:
7,405,477 →
Application:
11/292,685 →
User Registers Implemented with Routing Circuits in a Configurable Ic
Patent:
7,679,401 →
Application:
11/292,952 →
Users Registers in a Reconfigurable Ic
Patent:
7,489,162 →
Application:
11/293,856 →
Time Multiplexed Dynamic on-Die Termination
Using Dedicated Read Output Path to Reduce Unregistered Read Access Time for Fpga Embedded Memory
Patent:
7,414,916 →
Application:
11/303,734 →
Apparatus and Methods for Power Management in Integrated Circuits
Method of Reducing Leakage Current Using Sleep Transistors in Programmable Logic Device
Patent:
7,355,440 →
Application:
11/318,324 →
Distributed Memory in Field-Programmable Gate Array Integrated Circuit Devices
Functional Pre-Configuration of a Programmable Logic Device
Patent:
7,498,837 →
Application:
11/347,469 →
Dedicated Resource Interconnects
Patent:
7,368,942 →
Application:
11/351,882 →
Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Adjustable Transistor Body Bias Generation Circuitry with Latch-Up Prevention
Latch-Up Prevention Circuitry for Integrated Circuits with Transistor Body Biasing
System and Method for Providing More Logical Memory Ports Than Physical Memory Ports
Patent:
7,797,497 →
Application:
11/371,214 →
Booting Mechanism for Fpga-Based Embedded System
Patent:
7,822,958 →
Application:
11/372,532 →
Configurable Ic with Packet Switch Configuration Network
Patent:
7,375,550 →
Application:
11/375,362 →
Configuration Network for a Configurable Ic
Runtime Loading of Configuration Data in a Configurable Ic
Configurable Ic with Trace Buffer and/or Logic Analyzer Functionality
Checkpointing User Design States in a Configurable Ic
Random Access of User Design States in a Configurable Ic
Accessing Multiple User States Concurrently in a Configurable Ic
Programmable Phase-Locked Loop Circuitry for Programmable Logic Device
Techniques for Providing Flexible on-Chip Termination Control on Integrated Circuits
Techniques for Sensing Temperature and Automatic Calibration on Integrated Circuits
Patent:
7,410,293 →
Application:
11/383,937 →
Platform-Based Method and Apparatus for Containing Worms Using Multi-Timescale Heuristics
Communication signaling using multiple frequency bands in a wireless network
Application:
11/394,572 →
Publication:
US 2007/0099669
Flexible Ram Clock Enable
Patent:
7,397,726 →
Application:
11/399,771 →
Heterogeneous Transceiver Architecture for Wide Range Programmability of Programmable Logic Devices
Apparatus and Methods for Adjusting Performance Characteristics of Circuitry in Programmable Logic Devices
Application:
11/420,736 →
Publication:
US 2006/0202713
Apparatus and Methods for Adjusting Performance Characteristics and Power Consumption of Programmable Logic Devices
Semiconductor Module Comprising Components for Microwave Engineering in Plastic Casing and Method for the Production Thereof
Adder-Rounder Circuitry for Specialized Processing Block in Programmable Logic Device
Patent:
7,822,799 →
Application:
11/426,403 →
Dc Output Voltage Circuit with Substantially Flat Psrr
Patent:
7,471,138 →
Application:
11/431,340 →
Voltage-Controlled Oscillator Methods and Apparatus
Patent:
7,728,674 →
Application:
11/437,558 →
Voltage regulator with high noise rejection
Application:
11/441,849 →
Specialized Processing Block for Programmable Logic Device
Specialized Processing Block for Programmable Logic Device
Patent:
8,041,759 →
Application:
11/447,370 →
Specialized Processing Block for Programmable Logic Device
Specialized Processing Block for Programmable Logic Device
Patent:
8,301,681 →
Application:
11/447,474 →
Field Programmable Gate Array Architectures and Methods for Supporting Forward Error Correction
Patent:
7,869,343 →
Application:
11/447,745 →
Integrated stacked microchannel heat exchanger and heat spreader
Application:
11/453,428 →
Publication:
US 2006/0244127
System for Improving Memory Interface Data Integrity in Plds
Enhanced Data Converters Using Compression and Decompression
Patent:
7,292,164 →
Application:
11/462,687 →
Techniques for Providing Adjustable on-Chip Termination Impedance
Patent:
7,417,452 →
Application:
11/462,702 →
Apparatus and Methods for Multi-Gate Silicon-on-Insulator Transistors
Configurable Circuits, Ic's, and Systems
Processor core wear leveling in a multi-core platform
Application:
11/476,191 →
Publication:
US 2007/0300086
Highly Configurable Pll Architecture for Programmable Logic
Embedded Memory Data Transformation Circuitry
Patent:
8,392,674 →
Application:
11/490,747 →
Power-Aware Ram Processing
Patent:
7,877,555 →
Application:
11/510,018 →
Security Ram Block
Patent:
7,752,407 →
Application:
11/517,689 →
Semiconductor Device with a Plastic Housing Composition That Includes Filler Particles and That at Least Partially Embeds a Semiconductor Chip
Adapter Allowing Unaligned Access to Memory
Patent:
8,219,785 →
Application:
11/527,201 →
Memory Interface Phase-Shift Circuitry to Support Multiple Frequency Ranges
Patent:
8,188,781 →
Application:
11/531,263 →
Vpa Interconnect Circuit
Patent:
7,564,260 →
Application:
11/535,053 →
Configurable Logic Circuits with Commutative Properties
Apparatus and Methods for Adjusting Performance of Integrated Circuits
Efficient Delay Elements
Patent:
7,629,825 →
Application:
11/549,427 →
Cmos Device with Metal and Silicide Gate Electrodes and a Method for Making It
Enhanced Data Converters Using Compression and Decompression
Patent:
7,394,410 →
Application:
11/560,574 →
Method and System for Improving Memory Interface Data Integrity
Patent:
7,352,299 →
Application:
11/560,673 →
Configurable Circuits, Ic's, and Systems
Vpa Logic Circuits
Generating Cores Using Secure Scripts
Patent:
7,574,679 →
Application:
11/600,982 →
Omnibus Logic Element
Patent:
7,538,579 →
Application:
11/607,171 →
Non-Sequentially Configurable Ic
Configurable Circuits, Ic's and Systems
Power Supply Filtering for Programmable Logic Device Having Heterogeneous Serial Interface Architecture
Patent:
7,903,679 →
Application:
11/622,396 →
Clock Signal Circuitry for Multi-Protocol High-Speed Serial Interface Circuitry
Patent:
7,310,399 →
Application:
11/650,163 →
Next Generation 8B10B Architecture
Programmable Logic Device with on-Chip Nonvolatile User Memory
Patent:
7,550,994 →
Application:
11/668,325 →
Fractional Delay-Locked Loops
Patent:
7,675,332 →
Application:
11/669,845 →
Multiple Data Rate Memory Interface Architecture
Patent:
7,504,855 →
Application:
11/672,438 →
Programmable Logic Device Having Logic Array Block Interconnect Lines That Can Interconnect Logic Elements in Different Logic Blocks
Double exposure photolithographic process
Application:
11/710,650 →
Publication:
US 2007/0243492
Memory array circuitry with stability enhancement features
Application:
11/711,969 →
Soft Error Location and Sensitivity Detection for Programmable Devices
Megafunction Block and Interface
Patent:
7,724,598 →
Application:
11/737,654 →
Programmable Logic Device Having Redundancy with Logic Element Granularity
Method and Apparatus for Accessing Contents of Memory Cells
Structure for Electrostatic Discharge in Embedded Wafer Level Packages
Method and System for Using Boundary Scan in a Programmable Logic Device
Patent:
7,550,995 →
Application:
11/768,880 →
Leakage Compensation and Improved Setup/Hold Time in a Dynamic Flip-Flop
Patent:
7,893,726 →
Application:
11/782,443 →
H-Tree Driver Circuitry
Patent:
7,514,968 →
Application:
11/786,295 →
Low-Power Transceiver Architectures for Programmable Logic Integrated Circuit Devices
Patent:
7,403,035 →
Application:
11/788,561 →
High-Performance Memory Interface Circuit Architecture
Patent:
7,535,275 →
Application:
11/789,598 →
Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Semiconductor Device Encapsulated by an Electrically Conductive Plastic Housing Composition with Conductive Particles
Method for Fabricating a Semiconductor and Semiconductor Package
Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Write-Leveling Implementation in Programmable Logic Devices
Method and Apparatus for Reduced Power Cell
Semiconductor Device Including Switch That Conducts Based on Latched Bit and Next Bit
Patent:
7,474,243 →
Application:
11/854,849 →
Method and System for Gesture Classification
Variable Current Charge Pump with Modular Switch Circuit
Patent:
7,570,105 →
Application:
11/867,416 →
Semiconductor Module Including Components in Plastic Casing
High-Speed Charge Pump Circuits
Patent:
7,977,984 →
Application:
11/871,994 →
Configurable Clock Network for Programmable Logic Device
Patent:
7,646,237 →
Application:
11/888,336 →
Method for Isolating Third Party Pre-Boot Firmware from Trusted Pre-Boot Firmware
Flexible High-Speed Serial Interface Architectures for Programmable Integrated Circuit Devices
Patent:
7,602,212 →
Application:
11/904,003 →
Apparatus and Methods for Multi-Gate Silicon-on-Insulator Transistors
Pvt Compensated Auto-Calibration Scheme for DDR3
Patent:
7,590,008 →
Application:
11/936,036 →
Workpiece with Semiconductor Chips and Molding, Semiconductor Device and Method for Producing a Workpiece with Semiconductors Chips
Adjustable Transistor Body Bias Generation Circuitry with Latch-Up Prevention
Integrated Circuit Architectures with Heterogeneous High-Speed Serial Interface Circuitry
Patent:
7,759,972 →
Application:
11/981,934 →
Serializer-Deserializer Circuits Formed from Input-Output Circuit Registers
Patent:
7,587,537 →
Application:
11/998,603 →
Via Programmable Gate Array with Offset Direct Connections
Method of Reducing Leakage Current Using Sleep Transistors in Programmable Logic Device
Patent:
7,518,399 →
Application:
12/030,083 →
Enhanced Data Converters Using Compression and Decompression on a Single Integrated Circuit
Patent:
7,649,484 →
Application:
12/040,437 →
Omnibus Logic Element
Patent:
7,671,625 →
Application:
12/043,087 →
Latch-Up Prevention Circuitry for Integrated Circuits with Transistor Body Biasing
Normalization of Floating Point Operations in a Programmable Integrated Circuit Device
Patent:
8,244,789 →
Application:
12/048,379 →
Configurable Ic with Packet Switch Network
Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Application:
12/054,382 →
Publication:
US 2008/0164936
Techniques for Testing Memory Circuits
Patent:
7,761,754 →
Application:
12/055,099 →
Stacked Die Network-on-Chip for Fpga
Patent:
7,701,252 →
Application:
12/074,467 →
Techniques for Measuring Voltages in a Circuit
Runtime Loading of Configuration Data in a Configurable Ic
Techniques for Level Shifting Signals
Patent:
8,030,964 →
Application:
12/121,028 →
Charge Pump with Reduced Current Mismatch
Patent:
7,902,888 →
Application:
12/121,740 →
Static Random-Access Memory with Boosted Voltages
Phase-Locked Loop Circuitry with Multiple Voltage-Controlled Oscillators
Flexible Ram Clock Enable
Techniques for Providing Adjustable on-Chip Termination Impedance
Patent:
7,825,682 →
Application:
12/147,403 →
Ball Grid Array Package-to-Board Interconnect Co-Design Apparatus
Patent:
7,514,789 →
Application:
12/147,411 →
Distributed Memory in Field-Programmable Gate Array Integrated Circuit Devices
Dynamically-Adjustable Differential Output Drivers
Patent:
7,675,326 →
Application:
12/163,709 →
Digitally Controlled Oscillators
Apparatus and Methods for Power Management in Integrated Circuits
Debuggable Opaque Ip
Patent:
9,064,068 →
Application:
12/168,697 →
Volatile Memory Elements with Elevated Power Supply Levels for Programmable Logic Device Integrated Circuits
Using Dedicated Read Output Path to Reduce Unregistered Read Access Time for a Fpga Embedded Memory
Patent:
7,715,271 →
Application:
12/176,592 →
Memory with Addressable Subword Support
Patent:
7,916,572 →
Application:
12/181,311 →
Method of Mapping a User Design Defined for a User Design Cycle to an Ic with Multiple Sub-Cycle Reconfigurable Circuits
Systems, Methods, and Apparatuses for in-Band Data Mask Bit Transmission
Efficient Delay Elements
Data Encoding Scheme to Reduce Sense Current
Patent:
7,978,493 →
Application:
12/212,801 →
Low-Power Transceiver Architectures for Programmable Logic Integrated Circuit Devices
System and Process for Fabricating Semiconductor Packages
Debug Network for a Configurable Ic
Techniques for Generating Pvt Compensated Phase Offset to Improve Accuracy of a Locked Loop
Patent:
8,237,475 →
Application:
12/248,031 →
Integrated Circuits with Fuse Programming and Sensing Circuitry
Patent:
8,154,942 →
Application:
12/272,727 →
Bit Slip Circuitry for Serial Data Signals
Patent:
8,477,897 →
Application:
12/283,617 →
Advanced Multi-Channel Watermarking System and Method
Application:
12/300,566 →
Publication:
US 2010/0246810
Advanced Watermarking System and Method
System management mode isolation in firmware
Application:
12/317,446 →
Publication:
US 2009/0119748
Saturation and Rounding in Multiply-Accumulate Blocks
Application:
12/324,055 →
Publication:
US 2009/0100122
Memory Elements with Body Bias Control
Patent:
8,081,502 →
Application:
12/345,560 →
Multiple Data Rate Memory Interface Architecture
Patent:
7,994,816 →
Application:
12/368,308 →
Memory Elements with Increased Write Margin and Soft Error Upset Immunity
Patent:
7,920,410 →
Application:
12/391,230 →
Programmable Logic Device with Differential Communications Support
Patent:
7,958,416 →
Application:
12/393,018 →
Volatile Memory Elements with Minimized Area and Leakage Current
Patent:
8,081,503 →
Application:
12/395,598 →
Omnibus Logic Element for Packing or Fracturing
Patent:
7,911,230 →
Application:
12/425,342 →
Area-Efficient Memory Built-in-Self-Test Circuitry with Advanced Debug Capabilities for Distributed Memory Blocks
Patent:
8,004,915 →
Application:
12/463,358 →
High-Performance Memory Interface Circuit Architecture
Patent:
7,969,215 →
Application:
12/467,681 →
System and Method for Combining User and Platform Authentication in Negotiated Channel Security Protocols
Methods and systems for reducing interrupt latency by using a dedicated bit
Patent:
8,135,894 →
Application:
12/533,980 →
Charge Pump with Ramp Rate Control
Patent:
8,120,411 →
Application:
12/534,007 →
Apparatus and Methods for Adjusting Performance of Integrated Circuits
Mems Switching Device and Conductive Bridge Device Based Circuits
Patent:
8,130,559 →
Application:
12/535,395 →
Pvt Compensated Auto-Calibration Scheme for DDR3
Patent:
7,983,094 →
Application:
12/539,594 →
Techniques for Providing Multiple Delay Paths in a Delay Circuit
Patent:
7,893,739 →
Application:
12/549,332 →
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Memory Element Circuitry with Stressed Transistors
Patent:
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Memory Elements with Soft Error Upset Immunity
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Volatile Memory Elements with Soft Error Upset Immunity
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Heterogeneous Transceiver Architecture for Wide Range Programmability of Programmable Logic Devices
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Compression of Sampled Data in a Data Acquisition System
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Techniques for Configuring Multi-Path Feedback Loops
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Configurable Clock Network for Programmable Logic Device
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Integrated Circuits with Asymmetric and Stacked Transistors
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Techniques for Providing Reduced Duty Cycle Distortion
Techniques for motion estimation
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US 2011/0002387
Non-Sequentially Configurable Ic
Fractional Delay-Locked Loops
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User Registers Implemented with Routing Circuits in a Configurable Ic
Stacked Die Network-on-Chip for Fpga
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Phase-Locked Loop Architecture and Clock Distribution System
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Integrated Circuit Guard Ring Structures
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Techniques for on-Chip Termination
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Adaptive Clock Recovery with Step-Delay Pre-Compensation
Configuration Network for an Ic
Runtime Loading of Configuration Data in a Configurable Ic
Voltage Regulator with High Noise Rejection
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Application:
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Stacked Die Network-on-Chip for Fpga
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Voltage-Controlled Oscillator Methods and Apparatus
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Level Shifter Circuit with a Thin Gate Oxide Transistor
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Methods and Systems for Managing a Write Operation
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Security Ram Block
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Techniques for Testing Memory Circuits
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Methods and Systems for Measuring and Presenting Performance Data of a Memory Controller System
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Segmented Clock Network for Transceiver Array
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Memory Array Circuitry with Stability Enhancement Features
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Application:
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Configurable Memory Block
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Accessing Multiple User States Concurrently in a Configurable Ic
Memory Elements with Voltage Overstress Protection
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System and Method for Providing More Logical Memory Ports Than Physical Memory Ports
Booting Mechanism for Fpga-Based Embedded System
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SDRAM Memory Organization and Efficient Access
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Method for Fabricating a Semiconductor and Semiconductor Package
Memory Array with Redundant Bits and Memory Element Voting Circuits
Configurable Clock Network for Programmable Logic Device
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Forward Error Correction with Configurable Latency
Configurable Circuits, Ic's, and Systems
Memory Array with Distributed Clear Transistors and Variable Memory Element Power Supply
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Application:
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Power-Aware Ram Processing
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Trigger Circuits and Event Counters for an Ic
Charge Pump with Reduced Current Mismatch
Techniques for Providing Multiple Delay Paths in a Delay Circuit
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Delay Circuitry
Power Supply Filtering for Programmable Logic Device Having Heterogeneous Serial Interface Architecture
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Fabrication of Channel Wraparound Gate Structure for Field-Effect Transistor
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Omnibus Logic Element for Packing or Fracturing
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Memory Elements with Increased Write Margin and Soft Error Upset Immunity
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Trigger Circuits and Event Counters for an Ic
Non-Sequentially Configurable Ic
Setting Security Features of Programmable Logic Devices
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Apparatus and Methods for Adjusting Performance of Programmable Logic Devices
Static Random-Access Memory with Boosted Voltages
Heterogeneous Transceiver Architecture for Wide Range Programmability of Programmable Logic Devices
Techniques for Measuring Voltages in a Circuit
Integrated Circuits with Asymmetric Transistors
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Programmable Logic Device with Differential Communications Support
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Multiport Memory Element Circuitry
Methods for Calibrating Memory Interface Circuitry
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Memory Controllers with Dynamic Port Priority Assignment Capabilities
Memory Controller Interface with Adjustable Port Widths
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Data Encoding Scheme to Reduce Sense Current
Integrated Circuit Inductors with Intertwined Conductors
Saturation and Rounding in Multiply-Accumulate Blocks
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Memory Elements with a Configurable Number of Ports
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High-Performance Memory Interface Circuit Architecture
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Multiple Data Rate Memory Interface Architecture
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Method and System for Operating a Multi-Port Memory System
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Area-Efficient Memory Built-in-Self-Test Circuitry with Advanced Debug Capabilities for Distributed Memory Blocks
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Memory Elements with Elevated Control Signal Levels for Integrated Circuits
Systems and Methods for Providing Memory Controllers with Memory Access Request Merging Capabilities
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Digitally Controlled Oscillators
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Programmable Addressing Circuitry for Increasing Memory Yield
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First-In-First-Out Memory with Dual Memory Banks
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Runtime Loading of Configuration Data in a Configurable Ic
Configurable Clock Network for Programmable Logic Device
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3T Device Based Memory Circuits and Arrays
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Systems and Methods for Stacking a Memory Chip Above an Integrated Circuit Chip
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Logic Block Protection System
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Memory Elements with Relay Devices
Fast Parallel-to-Serial Memory Data Transfer System and Method
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Logic Device Having a Compressed Configuration Image Stored on an Internal Read Only Memory
User Registers Implemented with Routing Circuits in a Configurable Ic
Temperature Dependent Power Supply Circuitry
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Apparatus for Improving Power Consumption of Communication Circuitry and Associated Methods
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Write-Leveling Implementation in Programmable Logic Devices
Memory Circuit with PMOS Access Transistors
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Hierarchical Arbitration
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Transition Accelerator Circuitry
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Memory Circuitry with Dynamic Power Control
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Integrated Circuits with Multi-Stage Logic Regions
Memory Interface Phase-Shift Circuitry to Support Multiple Frequency Ranges
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Techniques for Measuring Voltages in a Circuit
Configurable Circuits, Ic's, and Systems
Integrated Circuit Package with Distributed Clock Network
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Digital Pvt Compensation for Delay Chain
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Application:
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Methods and Systems for Axi Id Compression
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Method for Fabricating a Semiconductor and Semiconductor Package
Phase-Locked Loop Architecture and Clock Distribution System
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Intelligent Spectrum Allocation Based on User Behavior Patterns
On-Demand Vacate Mechanism for Cloud Spectrum Services
Imt and Non-Imt Wireless Communication Device
Cloud-Based Spectrum Management Services
Operator and Third Party Cloud Spectrum Services for Efficient Spectrum Usage
Omnibus Logic Element for Packing or Fracturing
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Application:
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Normalization of Floating Point Operations in a Programmable Integrated Circuit Device
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Application:
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Configurable Clock Network for Programmable Logic Device
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Method for Fabricating a Semiconductor and Semiconductor Package
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
High Performance Memory Interface Circuit Architecture
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Application:
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Non-Sequentially Configurable Ic
Circuitry for Generating Peak Cancelling Pulses
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Trigger Circuits and Event Counters for an Ic
Multi-Chip Packages with Reduced Power Distribution Network Noise
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Methods and Apparatus for Memory Interface Systems
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Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips
Memory Interface Circuitry with Improved Timing Margins
Memory Interface Circuitry with Data Strobe Signal Sharing Capabilities
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Application:
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Delaying Start of User Design Execution
Patent:
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Application:
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Flip-Chip Wafer Level Package and Methods Thereof
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Application:
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System and Methods for Adjusting Memory Command Placement
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Application:
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Rom Device with Keepers
Forward Error Correction with Configurable Latency
Methods and Apparatus for Performing Boosted Bit Line Precharge
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System and Process for Fabricating Semiconductor Packages
Circuits and Methods for Dqs Autogating
Transceiver Circuitry with Multiple Phase-Locked Loops
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Application:
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Variable Gate Width Finfet
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Application:
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Chip package-in-package and method thereof
Methods and Apparatus for Performing Runtime Data Eye Monitoring and Continuous Data Strobe Calibration
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Advanced Watermarking System and Method
Patent:
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Application:
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Circuitry and Techniques for Image Processing
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Configurable Clock Network for Programmable Logic Device
Patent:
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Application:
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Bit Slip Circuitry for Serial Data Signals
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Method for Fabricating a Semiconductor Device and Semiconductor Package
Integrated Circuits with Asymmetric and Stacked Transistors
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Method for Reconfiguring an Erroneous Memory Frame in an Integrated Circuit
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Application:
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Multiple Data Rate Memory Interface Architecture
Supporting Pseudo Open Drain Input/Output Standards in a Programmable Logic Device
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Application:
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Integrated Circuit Package with Vacant Cavity
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Application:
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System and Method for Creating and Displaying Classes of Graphical Display Objects
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Publication:
US 2014/0245201
Speech Recognition Utilizing a Dynamic Set of Grammar Elements
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Publication:
US 2014/0244259
Method and Apparatus for Managing Dynamic Sharing of Spectrum Services
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Publication:
US 2015/0249926
Implementing a Dynamic Cloud Spectrum Database as a Mechanism for Cataloging and Controlling Spectrum Availability
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Publication:
US 2014/0256284
Phase-Locked Loop Architecture and Clock Distribution System
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Address Arithmetic on Block Rams
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Omnibus Logic Element
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Application:
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Methods and Circuitry for Identifying Logic Regions Affected by Soft Errors
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Application:
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Memory Circuit Including Memory Devices, a Freeze Circuit and a Test Switch
Patent:
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Reuse of Directory Entries for Holding State Information Through Use of Multiple Formats
Configurable Storage Circuits with Embedded Processing and Control Circuitry
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Application:
14/086,853 →
Memory Elements with Relay Devices
First-in First-out Circuits and Methods
Patent:
9,330,740 →
Application:
14/133,245 →
Forward Error Correction with Configurable Latency
Integrated Circuits with Asymmetric Transistors
Patent:
8,995,177 →
Application:
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Method for Fabricating a Semiconductor and Semiconductor Package
Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
Via Structure and Method for Its Fabrication
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Application:
14/158,646 →
Configuration Bit Architecture for Programmable Integrated Circuit Device
Configurable Clock Network for Programmable Logic Device
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Application:
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Methods for Packaging Integrated Circuits
User Registers Implemented with Routing Circuits in a Configurable Ic
Fused Floating Point Datapath with Correct Rounding
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Advanced Multi-Channel Watermarking System and Method
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Publication:
US 2014/0181991
Digital Pvt Compensation for Delay Chain
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Method for Manufacturing an Electronic Package
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Publication:
US 2014/0206142
Configurable Storage Blocks with Embedded First-in First-Out and Last-in First-Out Circuitry
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Application:
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Memory Elements With Soft Error Upset Immunity
Patent:
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Application:
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Method and Apparatus for Power Supply Aware Memory Access Operations in an Integrated Circuit
Patent:
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Application:
14/248,583 →
Setting Security Features of Programmable Logic Devices
Patent:
9,767,321 →
Application:
14/249,970 →
Lc Tank Circuitry with Shielding Structures
Patent:
9,646,759 →
Application:
14/251,364 →
Laterally Difffused Metal Oxide Semiconductor Device and Method of Forming the Same
Runtime Loading of Configuration Data in a Configurable Ic
Integrated Circuits with Asymmetric and Stacked Transistors
Memory Array with Redundant Bits and Memory Element Voting Circuits
System and Method for Improving Snoop Performance
Trigger Circuits and Event Counters for an IC
Apparatus and Methods for Power Management in Integrated Circuits
Application:
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Publication:
US 2014/0258956
Multiport Memory Element Circuitry
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Application:
14/297,063 →
Bit Slip Circuitry for Serial Data Signals
Patent:
9,054,854 →
Application:
14/300,892 →
Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips
Non-Sequentially Configurable IC
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14/331,191 →
Publication:
US 2015/0130508
Programmable Integrated Circuits with in-Operation Reconfiguration Capability
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9,299,396 →
Application:
14/331,470 →
Content Addressable Memory in Integrated Circuit
Circuits and Methods For Impedance Calibration
Patent:
9,369,128 →
Application:
14/461,048 →
Integrated Circuits Having Input-Output Circuits with Dedicated Memory Controller Circuitry
Patent:
9,330,218 →
Application:
14/473,978 →
Phase-Locked Loop Architecture and Clock Distribution System
Patent:
9,350,530 →
Application:
14/487,867 →
Omnibus Logic Element
Patent:
9,496,875 →
Application:
14/501,834 →
Clock Gating for System-on-Chip Elements
Embedded Interposer with Through-Hole Vias
Patent:
9,418,965 →
Application:
14/524,732 →
Integrated Circuit Voltage Regulator with Adaptive Current Bleeder Circuit
Patent:
9,917,513 →
Application:
14/559,833 →
Electrostatic Discharge Circuitry with Separate Power Rails
Patent:
9,368,485 →
Application:
14/563,620 →
Memory Cells with P-Type Diffusion Read-Only Port
Patent:
9,401,200 →
Application:
14/579,860 →
Device-To-Device (D2D) Communications
Apparatus and Method for Sense Amplifier Offset Cancellation
Patent:
9,384,791 →
Application:
14/586,549 →
System and Method for Visualization of Noc Performance Based on Simulation Output
Patent:
9,444,702 →
Application:
14/616,337 →
Runtime Loading of Configuration Data in a Configurable Ic
User Registers Implemented with Routing Circuits in a Configurable Ic
Memory Element Write-Assist Circuitry with Dummy Bit Lines
Patent:
10,236,055 →
Application:
14/668,842 →
Apparatus, System and Method of Communicating Data Between Awareness Networking Devices
Security Ram Block with Multiple Partitions
Application:
14/715,070 →
Publication:
US 2016/0248588
Forward Error Correction with Configurable Latency
Integrated Circuits with Embedded Double-Clocked Components
Liveness Detection Using Progressive Eyelid Tracking
Application:
14/749,193 →
Publication:
US 2016/0140390
Integrated Circuits with Guard Ring Structures for Nonplanar Transistor Devices
Patent:
9,530,835 →
Application:
14/837,992 →
State Visibility and Manipulation in Integrated Circuits
System and Process for Fabricating Semiconductor Packages
Methods for Initializing Memory Devices
Patent:
10,095,435 →
Application:
14/887,822 →
Delaying Start of User Design Execution
Patent:
10,354,706 →
Application:
14/949,145 →
Integrated Circuit with Overdriven and Underdriven Pass Gates
Patent:
10,121,534 →
Application:
14/974,015 →
Circuits and Methods for Dqs Autogating
Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips
Programmable Integrated Circuits with in-Operation Reconfiguration Capability
Patent:
9,607,671 →
Application:
15/061,440 →
Chip Package-In-Package
Fused Floating Point Datapath with Correct Rounding
Patent:
9,552,190 →
Application:
15/133,363 →
Phase-Locked Loop Architecture and Clock Distribution System
Patent:
9,654,123 →
Application:
15/138,749 →
Memory Elements with Dynamic Pull-Up Weakening Write Assist Circuitry
Patent:
9,767,892 →
Application:
15/140,188 →
Circuits and Methods For Impedance Calibration
Patent:
9,680,469 →
Application:
15/156,309 →
Emulated Multiport Memory Element Circuitry with Exclusive-or Based Control Circuitry
Address Arithmetic on Block Rams
Patent:
9,837,133 →
Application:
15/177,088 →
Phase-Locked Loops with Electrical Overstress Protection Circuitry
Methods for Packaging Integrated Circuits
Methods and Apparatus for Smart Memory Interface
Fabrication of Channel Wraparound Gate Structure for Field-Effect Transistor
Application:
15/197,563 →
Publication:
US 2016/0308014
Lutram Dummy Read Scheme During Error Detection and Correction
Patent:
10,191,661 →
Application:
15/228,989 →
Apparatus For Improving Power Consumption Of Communication Circuitry And Associated Methods
Memory Interface Circuitry with Distributed Data Reordering Capabilities
Patent:
10,282,109 →
Application:
15/266,646 →
Circuitry for Reducing Leakage Current in Configuration Memory
Systems and Methods for Refreshing Data in Memory Circuits
Patent:
9,934,841 →
Application:
15/299,653 →
Omnibus Logic Element
Patent:
10,177,766 →
Application:
15/351,167 →
Variable Gate Width Finfet
Patent:
9,698,252 →
Application:
15/356,278 →
Clock Gating for System-on-Chip Elements
Security Ram Block with Multiple Partitions
Patent:
10,970,409 →
Application:
15/389,886 →
Programmable Integrated Circuits with in-Operation Reconfiguration Capability
Circuits and Methods For Impedance Calibration
Application:
15/583,418 →
Publication:
US 2017/0237433
State Visibility and Manipulation in Integrated Circuits
Circuits and Methods for Dqs Autogating
Application:
15/614,221 →
Publication:
US 2017/0270995
Supporting Pseudo Open Drain Input/Output Standards in a Programmable Logic Device
Setting Security Features of Programmable Logic Devices
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Memory Interface Circuitry with Distributed Data Reordering Capabilities
Method for Fabricating a Semiconductor and Semiconductor Package
Method for Fabricating a Semiconductor and Semiconductor Package
Interactive system
Application:
60/349,671 →
System and method for providing usage metrics of digital content
Application:
60/455,466 →
Configurable integrated circuits with programmable vias
Application:
60/560,747 →
Method and apparatus pertaining to software-based security coprocessors
Application:
60/681,094 →
Method and apparatus for authoring and managing multimedia documents
Application:
60/689,345 →
Multi-modal knowledge synthesis and retrieval system
Application:
60/689,613 →
Information services for real world augmentation
Application:
60/689,618 →
Multi-modal context marketplace
Application:
60/689,741 →
Computer information presentation system
Application:
60/689,743 →
Configuration and debug network for configurable ICs
Application:
60/699,463 →
System for providing information services relevant to visual imagery
Application:
60/705,220 →
User interface for providing information services relevant to visual imagery
Application:
60/715,529 →
Method and system for distributed e-commerce
Application:
60/715,979 →
Enhancements for system for providing information services relevant to visual imagery
Application:
60/716,874 →
Power-aware RAM processing
Application:
60/719,251 →
System and method for providing digital content on mobile devices
Application:
60/724,821 →
Frame format structures for communication within a wireless network using two frequency bands
Application:
60/730,575 →
Method to provide floating point arithmetic functions for FPGA
Application:
60/771,988 →
Method to implement rounding and saturation function for DSP applications in FPGA
Application:
60/771,989 →
Flexible hardwired DSP block for FPGA devices
Application:
60/772,197 →
Method to perform filtering and other DSP functions in FPGA
Application:
60/772,465 →
Techniques for sensing temperature and automatic calibration on integrated circuits
Application:
60/786,129 →
Specialized processing block for program mable logic device
Application:
60/789,535 →
Techniques for providing flexible on-chip termination control on integrated circuits
Application:
60/789,760 →
Double exposure photo lithographic process
Application:
60/792,038 →
Soft error location and sensitivity detection for PLDs
Application:
60/793,946 →
Write-leveling implementation in programmable logic devices
Application:
60/840,107 →
PVT compensated dynamic auto-calibration scheme for simplifying high performance DDR3 memory interface design in FPGAs
Application:
60/857,467 →
Advanced Two-Stage Transactional Audio Watermarking
Application:
60/956,545 →
Stacked die network-on chip for FPGA
Application:
61/002,162 →
Intelligent Mobile GIS System and Method
Application:
61/034,675 →
GUI for Tracking Data Values in an IC
Application:
61/086,145 →
Memory Elements with Soft Error Upset Immunity for Integrated Circuits
Application:
61/102,000 →
Memory Elements with Controllable Inverter Circuitry
Application:
61/102,003 →
Volatile Memory Elements with Soft Error Upset Immunity
Application:
61/113,573 →
Memory Elements with Soft Error Upset Immunity
Application:
61/120,334 →
Cantilever device and 3T device based memory circuits and multiplexers
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61/188,081 →
Adaptive Clock Recovery
Application:
61/292,534 →
Advanced eXtensible Interface (AXI) ID Compression Scheme
Application:
61/539,602 →
High-Speed, Low-Area Arbitration
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61/544,951 →
Content Addressable Memory in an Integrated Circuit
Application:
61/558,984 →
Cppc, Rasf, Mpst, Fpdt, and Einj Technology
Application:
61/563,030 →
Delayed Start of User Design
Application:
61/576,972 →
Intelligent Spectrum Allocation Based on User Behavior Patterns for Efficient Spectrum Usage
Application:
61/603,261 →
Advanced Wireless Communication Systems and Techniques
Application:
61/820,021 →
Integrated Circuits Having Input-Output Circuits with Dedicated Memory Controller Circuitry
Application:
61/873,268 →
Area Efficient and Highspeed Esd Protection Scheme
Application:
61/925,796 →
Rrc Connection Establishment for D2D Communication
Application:
61/990,679 →
Network Controlled Autonomous Handover
Application:
62/027,170 →
One Measurement Gap in Asynchronous Dc
Application:
62/035,092 →
Access Control Mechanism for D2D Discovery and Communication
Application:
62/055,598 →
Liveness Detection in Facial Recognition with Spoof-Resistant Progressive Eyelid Tracking
Application:
62/079,011 →
Covert Liveness Detection System and Method
Application:
62/079,036 →
Facial Spoofing Detection Facilitation
Application:
62/079,044 →
Eyelid Tracking for Biometric Live-Ness Test
Application:
62/079,095 →
Spoofing Detection in Image Based Biometrics
Application:
62/079,102 →
Memory Element Write-Assist Circuitry with Dummy Bit Lines
Application:
62/091,423 →
Apparatus, System and Method of Communicating Data Between Awareness Networking Devices
Application:
62/100,991 →
Method to Initialize a Memory Device
Application:
62/101,842 →
Apparatus, System and Method of Geo-Fencing in Awareness Networking
Application:
62/107,548 →
Apparatus, System and Method of Dynamic Allocation Using a Grant Frame
Application:
62/119,200 →
Latency Reduction for Data Transmission in Wireless System
Application:
62/248,997 →
Smart Parking System
Application:
62/363,057 →
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Application:
62/393,465 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 7, 2012
From: QLOGIC CORPORATION
To: INTEL CORPORATION
Reel/Frame 028168/0202 →
Assignment of Assignor's Interest
Jan 19, 2017
From: TEXAS INSTRUMENTS INCORPORATED
To: INTEL CORPORATION
Reel/Frame 041383/0040 →
Security Interest
Nov 26, 2019
From: CLOUDLEAF, INC.
To: VENTURE LENDING & LEASING IX, INC.; VENTURE LENDING & LEASING VIII, INC.
Reel/Frame 051139/0777 →
Assignment of Assignor's Interest
Jul 20, 2022
From: ALTERA CORPORATION
To: INTEL CORPORATION
Reel/Frame 060778/0032 →
Security Interest
Mar 28, 2023
From: PARKOURSC, INC., PREVIOUSLY KNOWN AS CLOUDLEAF, INC.
To: WTI FUND X, INC.
Reel/Frame 063136/0153 →