Structure for electrostatic discharge in embedded wafer level packages
View Patent ↗A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
1. A method for producing a workpiece, comprising:
providing at least two semiconductor chips each having a first main surface and a second main surface;
placing the semiconductor chips with their first main surfaces on the upper side of a carrier sheet;
applying an electrically conducting layer to regions of the second main surfaces, the electrically conducting layer being in the form of a grid structure comprising rows and columns of electrically conducting material, with the semiconductor chips being respectively arranged at intersecting points of the rows and columns;
applying a molding compound to the electrically conducting layer; and
removing the carrier sheet, thereby exposing the first main surface of the semiconductor chips and molding compound that is co-planar with the first main surface of the semiconductor chips.
2. The method of claim 1 , further comprising applying the electrically conducting layer to regions of an upper side of the carrier sheet in interspaces between the semiconductor chips.
3. The method of claim 1 , further comprising applying the electrically conducting layer to side faces of the semiconductor chips.
4. The method of claim 1 , further comprising applying the electrically conducting layer by printing on a conductive polymer or a conductive ink.
5. The method of claim 1 , further comprising applying the electrically conducting layer by vapor-depositing.
6. The method of claim 1 , further comprising applying the electrically conducting layer by sputtering.
7. The method of claim 1 , further comprising arranging the electrically conducting layer such that the semiconductor chips are connected to one another in an electrically conducting manner.
8. The method of claim 1 , further comprising applying an insulating layer of an electrically insulating material to regions of the semiconductor chips before applying the electrically conducting layer.
9. The method of claim 8 , further comprising vapor-depositing the insulating layer.
10. The method of claim 8 , further comprising placing the insulating layer on an electrically insulating film.
11. The method of claim 1 , further comprising
dividing up the panel into semiconductor devices along dicing tracks.
12. The method of claim 1 , further comprising applying the electrically conducting layer such that the grid structure is made up a number of partial regions that are insulated from one another.
13. The method of claim 12 , wherein one partial region comprises a predetermined row or a plurality of predetermined rows of the grid structure.
14. The method of claim 12 , wherein one partial region comprises a predetermined column or a plurality of predetermined columns of the grid structure.