Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same

1. An integrated circuit capable of being used with a power converter, comprising:

a transistor capable of being used as a power switch of a power train of said power converter, including:

a gate located over a channel region recessed into a semiconductor substrate,

a source/drain including a lightly doped region adjacent said channel region,

an oppositely doped well extending under said channel region and a portion of said lightly doped region of said source/drain,

a doped region adjacent said oppositely doped well and extending under a portion of said lightly doped region of said source/drain;

an oppositely doped buried layer under said doped region; and

a channel extension, within said oppositely doped well, under said channel region and extending under a portion of said lightly doped region of said source/drain; and

a driver switch of a driver formed on said semiconductor substrate and configured to provide a drive signal to said transistor.

2. The integrated circuit as recited in claim 1 wherein said channel extension extends under said portion of said lightly doped region of said source/drain by a channel extension length.

3. The integrated circuit as recited in claim 1 wherein said channel extension is of like type to and has a doping concentration profile greater than a doping concentration profile of said oppositely doped well.

4. The integrated circuit as recited in claim 1 wherein said source/drain includes a heavily doped region adjacent said lightly doped region of said source/drain.

5. The integrated circuit as recited in claim 1 wherein said source/drain includes a heavily doped region adjacent but not surrounded by said lightly doped region of said source/drain.

6. The integrated circuit as recited in claim 1 wherein said source/drain includes a heavily doped region adjacent said lightly doped region, said transistor further comprising an isolation region adjacent said heavily doped region of said source/drain.

7. The integrated circuit as recited in claim 1 wherein said transistor further comprises another source/drain having a lightly doped region adjacent an opposing side of said channel region, said channel extension extending under a portion of said lightly doped region of said another source/drain by a channel extension length.

8. The integrated circuit as recited in claim 1 wherein said transistor further comprises another source/drain having a heavily doped region adjacent an opposing side of said channel region, said channel extension extending under a portion of said heavily doped region of said another source/drain by a channel extension length.

9. The integrated circuit as recited in claim 1 wherein said said channel extension extends under only a portion of said lightly doped region of said source/drain.

10. The integrated circuit as recited in claim 1 wherein said transistor further comprises a gate dielectric layer underlying said gate and gate sidewall spacers formed about said gate, said transistor further comprising metal contacts formed over a salicide layer formed on said gate and said source/drain.

11. The integrated circuit as recited in claim 1 wherein said oppositely doped buried layer has a doping concentration profile in a range of 1·10 18 to 1·10 20 atoms/centimeter 3 .

12. The integrated circuit as recited in claim 1 wherein said oppositely doped well has a retrograde doping concentration profile with about 1·10 17 atoms/centimeter 3 in a middle area thereof.

13. The integrated circuit as recited in claim 1 wherein said oppositely doped well has a retrograde doping concentration profile with higher doping concentration profile at a top surface compared to a middle area thereof.

14. The integrated circuit as recited in claim 1 wherein said channel extension has a doping concentration profile of about 1.2·10 18 atoms/centimeter 3 .

15. The integrated circuit as recited in claim 1 wherein said lightly doped region of said source/drain has a doping concentration profile in a range of 1·10 16 to 1·10 17 atoms/centimeter 3 .

16. The integrated circuit as recited in claim 1 wherein said gate has a thickness in a range from about 100 to 500 nanometers.

17. The integrated circuit as recited in claim 1 wherein said doped region has a doping concentration profile in a range of 1·10 14 to 1·10 16 atoms/centimeter 3 .

18. The integrated circuit as recited in claim 1 wherein said channel extension extends under said portion of said lightly doped region of said source/drain by a channel extension length, said channel extension length being selected to provide an increased breakdown voltage and reduced on-state resistance for a laterally diffused metal oxide semiconductor device.

19. The integrated circuit as recited in claim 1 wherein said channel extension extends under said portion of said lightly doped region of said source/drain by about 0.3 micrometers, a channel extension dose is about 1·10 13 centimeters −2 , a channel extension energy is about 160 kilovolts, and a length and dose of said lightly doped region of said source drain is about 0.6 micrometers and 5·10 12 centimeters −2 , respectively.

20. The integrated circuit as recited in claim 1 wherein lightly doped region of said source/drain and said doped region are P-type, and said oppositely doped well, channel extension and oppositely doped buried layer are N-type.