Method for fabricating a semiconductor and semiconductor package
View Patent ↗A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
1. A semiconductor chip package, comprising:
at least one semiconductor chip comprising a contact pads on a first surface of the semiconductor chip;
a material layer covering at least partially the semiconductor chip, other than the first surface of the semiconductor chip; and
a dielectric layer disposed above the first surface of the semiconductor chip, wherein the dielectric layer comprises a material with at least one additive, wherein the at least one additive releases a catalytic starter or an electrically conducting material upon irradiation.
2. The semiconductor chip package of claim 1 , wherein the dielectric layer comprises a plurality of vias aligned with the plurality of contact pads, wherein the plurality of vias are filled with conductive material.
3. The method of claim 2 , wherein the conductive material comprises conductive ink.
4. The semiconductor chip package of claim 1 , further comprising:
a wiring layer comprising a contact area connected with the plurality of vias.
5. The semiconductor chip package of claim 4 , further comprising:
a solder resist layer applied above the wiring layer, the solder resist layer comprising an opening in which the contact area is exposed.
6. The semiconductor chip package of claim 4 , further comprising:
a solder ball applied above the opening of the solder resist layer, the solder ball being electrically connected with the contact area.