IP Library Granted Patent US 7,430,265
Granted Patent B2
US 7,430,265 · App. 11/018,379 · Granted Sep 30, 2008

Circuit arrangement provided with a phase-locked loop and transmitter-receiver with said circuit arrangement

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Quick Facts
Patent No.
US 7,430,265
App. No.
11/018,379
Granted
Sep 30, 2008
Kind
B2
Abstract

The invention specifies a circuit arrangement with a phase locked loop ( 1 ), which can be used as a mobile radio transmitter, in particular. The reference frequency for the PLL ( 1 ), which is provided by means of the source ( 3 ), is multiplied by a multiplier ( 10 ) and is down-converted to an intermediate-frequency level in a down-conversion mixer ( 9 ) using the output signal from the PLL, and is evaluated such that a modulator ( 13 ) connected to the input of the oscillator ( 6 ) can be trimmed. The inventive principle is used to advantage in two-point modulators and allows inexpensive, integratable mobile radio transmitters with good noise characteristics.

Claims (26)

1. A circuit arrangement with a phase locked loop comprising:

a reference source that provides a reference signal at a reference frequency;

a phase detector having a first input connected to the reference source, a second input and an output;

an oscillator having a control input coupled to the output of the phase detector and an output coupled to the second input of the phase detector;

a modulator having an output and a control input, wherein the output provides a modulation signal to the control input of the oscillator; and

a trimming path for trimming the modulator comprising a frequency mixer having a first input coupled to the output of the oscillator, a second input coupled to the reference source, and an output coupled to the control input of the modulator via a demodulator.

2. The circuit arrangement of claim 1 , wherein the output of the oscillator is coupled to the second input of the phase detector by providing a frequency divider for the purpose of dividing down an output signal from the oscillator.

3. The circuit arrangement of claim 2 , wherein the frequency divider has a control input to supply the modulation signal in digitally coded form.

4. The circuit arrangement of claim 1 , further comprising a frequency multiplier that couples the second input of the frequency mixer to the reference source, wherein the frequency multiplies the reference frequency.

5. The circuit arrangement of claim 1 , further comprising an evaluation unit that couples the demodulator to the control input of the modulator.

6. The circuit arrangement of claim 1 , further comprising a low-pass filter coupled to the demodulator and an evaluation unit coupled to the demodulator and the modulator.

7. The circuit arrangement of claim 1 , further comprising a switch connected to the demodulator, a bandpass filter connected to the switch, and an evaluation unit connected to the bandpass filter and the modulator, wherein a passband of the bandpass filter matches the frequency of the periodic signal generated by a test data generator.

8. The circuit arrangement of claim 1 , further comprising a bandpass filter connected to the demodulator and an evaluation unit connected to the bandpass filter and the modulator, wherein a passband of the bandpass filter matches the frequency of the periodic signal generated by a test data generator.

9. The circuit arrangement of claim 1 , wherein the oscillator is a voltage controlled oscillator and the circuit arrange further comprises a charge pump, a loop filter, and a summing node, wherein the charge pump is connected to the output of the phase detector, the loop filter is connected to the charge pump, the summing node has a first input connected to the loop filter and an output connected to the control input of the oscillator.

10. The circuit arrangement of claim 8 , wherein a second input of the summing node is connected to the output of the modulator.

11. The circuit arrangement of claim 1 , further comprising a test data generator that generates a periodic signal and has an output connected to an input of the modulator, wherein the modulator generates a demodulated signal according to the periodic signal and provides the demodulated signal to a further input of the oscillator.

12. A transceiver comprising:

a circuit arrangement with a phase locked loop comprising:

a reference source that provides a signal at a reference frequency;

a phase detector having a first input connected to the reference source, a second input and an output;

an oscillator having a control input coupled to the output of the phase detector and an output coupled to the second input of the phase detector;

a modulator having an output and an input, wherein the output provides a modulation signal to the control input of the oscillator; and

a trimming path for trimming the modulator comprising a frequency mixer having a first input coupled to the output of the oscillator, a second input coupled to the reference source, and an output coupled to the control input of the modulator via a demodulator;

a transmission path for transmitting a modulated signal which contains the circuit arrangement with a phase locked loop operating as a direct modulator; and

a reception path for receiving a modulated signal which contains the demodulator.

13. The circuit arrangement of claim 1 , wherein the reference source is configured to generate the reference signal as an unmodulated reference signal.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061827/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2005
From: CONVENT, THOMAS; HAMMES, MARKUS; HANKE, ANDRE; PUMA, GIUSEPPE LI; MEVISSEN, WALTER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016552/0188 →