Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same

1. A transistor, comprising:

a semiconductor substrate;

a channel region recessed into said semiconductor substrate;

a gate located over said channel region;

a source/drain including a doped region adjacent said channel region;

another source/drain including a doped region adjacent an opposing side of said channel region;

an oppositely doped well under said channel region and said doped region of said source/drain; and

a channel extension, within said oppositely doped well, under at least a portion of said channel region and extending under at least a portion of said doped region of said source/drain and at least a portion of said doped region of said another source/drain.

2. The transistor as recited in claim 1 wherein said channel extension extends under said portion of said doped region of said source/drain by a channel extension length.

3. The transistor as recited in claim 1 wherein said channel extension is of like type to said oppositely doped well.

4. The transistor as recited in claim 1 wherein said channel extension has a doping concentration profile greater than a doping concentration profile of said oppositely doped well.

5. The transistor as recited in claim 1 wherein said channel extension has a doping concentration greater than a doping concentration profile of said channel region.

6. The transistor as recited in claim 1 wherein said doped regions of said source/drain and said another source/drain are P-type.

7. The transistor as recited in claim 6 wherein said channel extension and said oppositely doped well are N-type.

8. The transistor as recited in claim 1 wherein said doped region of said source/drain is a lightly doped region and said doped region of said another source/drain is a lightly doped region.

9. The transistor as recited in claim 1 wherein said doped region of said source/drain is a lightly doped region and said doped region of said another source/drain is a heavily doped region.

10. The transistor as recited in claim 1 wherein said doped region of said source/drain is a lightly doped region.

11. The transistor as recited in claim 10 wherein said channel extension extends under said portion of said lightly doped region of said source/drain by a channel extension length.

12. The transistor as recited in claim 10 wherein said source/drain includes a heavily doped region adjacent but not surrounded by said lightly doped region of said source/drain.

13. The transistor as recited in claim 10 wherein said source/drain includes a heavily doped region adjacent said lightly doped region of said source/drain.

14. The transistor as recited in claim 13 further comprising a doped region extending between said heavily doped region of said source/drain and said oppositely doped well.

15. The transistor as recited in claim 13 further comprising a doped region extending between said heavily doped region of said source/drain and said oppositely doped well and an oppositely doped buried layer under said doped region.

16. The transistor as recited in claim 1 wherein said doped region of said source/drain is a heavily doped region.

17. The transistor as recited in claim 16 wherein said channel extension extends under said portion of said heavily doped region of said source/drain by a channel extension length.

18. The transistor as recited in claim 1 further comprising a gate dielectric layer underlying said gate and gate sidewall spacers formed about said gate.

19. The transistor as recited in claim 1 further comprising metal contacts formed over a salicide layer formed on said gate and said source/drain.

20. The transistor as recited in claim 1 wherein said oppositely doped well has a retrograde doping concentration profile with higher doping concentration profile at a top surface and a bottom surface compared to a middle area thereof.