Clock gating for system-on-chip elements
View Patent ↗An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.
1. A hardware element in a Network on Chip (NoC) and/or System on Chip (SoC) comprising:
a clock gating circuit that configures one or more neighboring hardware elements to activate before receiving new incoming data; and to configure the one or more neighboring hardware elements to sleep after a defined number of cycles, said defined number of cycles are counted from a cycle having non-receipt of incoming data and having a clearance of all data within an input queue of a source hardware element, the defined number of cycles being set based on at least one of a predetermined number of cycles and a calculation based on a self-learning process associated with one or more conditions of the at least one of the SoC and the NoC;
wherein the hardware element is configured to be clock gated or clock disabled through one of a system level signal and a programmed register, upon which hardware element sends interrupt to its neighboring hardware elements to prevent them from sending messages to the hardware element.
2. The hardware element of claim 1 , wherein the clock gating circuit is configured to transmit advance wake up notification to one or more adjacent hardware elements, the notification comprising at least one of a signal and a message.
3. The hardware element of claim 2 , wherein the clock gating circuit is configured to extract information regarding a subsequent hop for incoming data, and transmit said wake up notification only to a hardware element associated with the subsequent hop.
4. The hardware element of claim 1 , wherein the number of cycles is configured based on a hysteresis counter for reducing latency penalty due to clock gating and for saving power.
5. The hardware element of claim 4 , wherein the hysteresis counter value is configured to be set via self-learning based on network traffic and at least one of the SoC and the NoC conditions, wherein the self-learning applies self-correction to the number of cycles.
6. The hardware element of claim 1 , wherein the clock gating circuit uses a window of predetermined number of cycles for information across synchronous and asynchronous clock boundaries with neighboring agents to stabilize, before making clock gating decisions.
7. The hardware element of claim 1 , wherein the clock gating circuit is configured to be overridden.
8. The hardware element of claim 7 , wherein the override can be in form of a local override, and is implemented in form of a programmable internal register or a signal or a combination thereof.
9. The hardware element of claim 7 , wherein the override can be in form of a global override for clock gating circuit provisioned through an external register or a signal.
10. A semiconductor device comprising a Network on Chip (NoC), said NoC comprising:
a clock gating circuit configured in a hardware element of said NoC, said clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data; and to configure the one or more neighboring hardware elements to sleep after a defined number of cycles, said defined number of cycles are counted from a cycle having non-receipt of incoming data and having a clearance of all data within an input queue of a source hardware element, the defined number of cycles being set based on at least one of a predetermined number of cycles and a calculation based on a self-learning process associated with one or more conditions of the NoC;
wherein the hardware element is configured to be clock gated or clock disabled through one of a system level signal and a programmed register, upon which hardware element sends interrupt to its neighboring hardware elements to prevent them from sending messages to the hardware element.
11. The semiconductor device of claim 10 , wherein the clock gating circuit is configured to transmit advance wake up notification to one or more adjacent hardware elements, the notification comprising at least one of a signal and a flit.
12. The semiconductor device of claim 11 , wherein the clock gating circuit is configured to extract information regarding a subsequent hop for incoming data, and transmit said wake up notification only to a hardware element associated with the subsequent hop.
13. The semiconductor device of claim 10 , wherein the number of cycles is configured based on a hysteresis counter for reducing latency penalty due to clock gating and for saving power.
14. The semiconductor device of claim 13 , wherein the hysteresis counter value is configured to be set via self-learning based on network traffic and NoC conditions, wherein the self-learning applies self-correction to the number of cycles.
15. The semiconductor device of claim 10 , wherein the clock gating circuit uses a window of predetermined number of cycles for information across synchronous and asynchronous clock boundaries with neighboring agents to stabilize, before making clock gating decisions.
16. The semiconductor device of claim 10 , wherein the clock gating circuit is configured to be overridden based on a specification of a route on NoC, from system level.