Patent Assignment
Reel/Frame 060753/0662
Assignment of Assignor's Interest
Recorded: 2022-07-19
Pages: 12
Assignor
NETSPEED SYSTEMS, INC.
Executed: 2022-07-08
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(117)
Automatic Construction of Deadlock Free Interconnects
Heterogeneous Channel Capacities in an Interconnect
ASYMMETRIC MESH NoC TOPOLOGIES
Patent:
8,601,423 →
Application:
13/658,663 →
Hierarchical Asymmetric Mesh with Virtual Routers
Tagging and Synchronization for Fairness in Noc Interconnects
Automatic Deadlock Detection and Avoidance in a System Interconnect by Capturing Internal Dependencies of Ip Cores Using High Level Specification
Qos in Heterogeneous Noc by Assigning Weights to Noc Node Channels and Using Weighted Arbitration at Noc Nodes
Creating Multiple Noc Layers for Isolation or Avoiding Noc Traffic Congestion
Automatically Connecting Socs Ip Cores to Interconnect Nodes to Minimize Global Latency and Reduce Interconnect Cost
Application:
13/779,618 →
Reconfigurable Noc for Customizing Traffic and Optimizing Performance After Noc Synthesis
Multiple Heterogeneous Noc Layers
Heterogeneous Soc Ip Core Placement in an Interconnect to Optimize Latency and Interconnect Performance
Congestion Control and Qos in Noc by Regulating the Injection Traffic
Multiple Clock Domains in Noc
Identification of Internal Dependencies Within System Components for Evaluating Potential Protocol Level Deadlocks
Application:
13/942,332 →
System Level Simulation in Network on Chip Architecture
Automatic Noc Topology Generation
Supporting Multicast in Noc Interconnect
Automatically Connecting Socs Ip Cores to Interconnect Nodes to Minimize Global Latency and Reduce Interconnect Cost
Patent:
8,667,439 →
Application:
13/961,809 →
Combining Associativity and Cuckoo Hashing
Identification of Internal Dependencies Within System Components for Evaluating Potential Protocol Level Deadlocks
Asymmetric Mesh Noc Topologies
Asymmetric Mesh Noc Topologies
Noc Interface Protocol Adaptive to Varied Host Interface Protocols
Application:
14/054,667 →
Publication:
US 2015/0103822
Using Multiple Traffic Profiles to Design a Network on Chip
Reuse of Directory Entries for Holding State Information Through Use of Multiple Formats
Automatic Pipelining of Noc Channels to Meet Timing and/or Performance
Streaming Bridge Design with Host Interfaces and Network on Chip (Noc) Layers
Cache Coherent Noc with Flexible Number of Cores, I/O Devices, Directory Structure and Coherency Points
Application:
14/144,321 →
Publication:
US 2015/0186277
Qos in a System with End-to-End Flow Control and Qos Aware Buffer Allocation
Integrated Noc for Performing Data Communication and Noc Functions
Systems and Methods for Selecting a Router to Connect a Bridge in the Network on Chip (Noc)
System and Method for Improving Snoop Performance
Transactional Traffic Specification for Network-on-Chip Design
Using Cuckoo Movement for Improved Cache Coherency
Asymmetric Mesh Noc Topologies
Application:
14/334,019 →
Publication:
US 2014/0331027
Automatic Performance Characterization of a Network-on-Chip (Noc) Interconnect
Configurable Router for a Network on Chip (Noc)
Specification for Automatic Power Management of Network-on-Chip and System-On-Chip
Patent:
9,477,280 →
Application:
14/495,689 →
Automatic Generation of Power Management Sequence in a Soc or Noc
Clock Gating for System-on-Chip Elements
Heterogeneous Channel Capacities in an Interconnect
Automatic Power Domain and Voltage Domain Assignment to System-on-Chip Agents and Network-on-Chip Elements
Patent:
9,529,400 →
Application:
14/527,463 →
Automatic Buffer Sizing for Optimal Network-on-Chip Design
System and Method for Visualization of Noc Performance Based on Simulation Output
Patent:
9,444,702 →
Application:
14/616,337 →
Transaction Expansion for Noc Simulation and Noc Design
Hardware and Software Enabled Implementation of Power Profile Management Instructions in System on Chip
Generation of Network-on-Chip Layout Based on User Specified Topological Constraints
Dynamically Configuring Store-and-Forward Channels and Cut-Through Channels in a Network-On-Chip
Automatic Generation of Physically Aware Aggregation/Distribution Networks
Verification Low Power Collateral Generation
System and Method for Grouping of Network on Chip (Noc) Elements
Application:
14/743,749 →
Publication:
US 2017/0063626
Generating Physically Aware Network-on-Chip Design from a Physical System-on-Chip Specification
Hierarchical Asymmetric Mesh with Virtual Routers
Automatic Pipelining of Noc Channels to Meet Timing and/or Performance
Patent:
9,569,579 →
Application:
14/789,401 →
Automatic Pipelining of Noc Channels to Meet Timing and/or Performance
Heterogeneous Soc Ip Core Placement in an Interconnect to Optimize Latency and Interconnect Performance
Integrated Noc for Performing Data Communication and Noc Functions
Qos in a System with End-to-End Flow Control and Qos Aware Buffer Allocation
System Level Simulation in Network on Chip Architecture
Supporting Multicast in Noc Interconnect
Hardware and Software Enabled Implementation of Power Profile Management Instructions in System on Chip
Clock Gating for System-on-Chip Elements
System and Method for Network on Chip Construction Through Machine Learning
CONGESTION CONTROL AND QoS IN NoC BY REGULATING THE INJECTION TRAFFIC
Application:
15/392,154 →
Publication:
US 2017/0111283
Buffer Sizing of a Noc Through Machine Learning
Strategies for NoC Construction Using Machine Learning
Application:
15/403,162 →
Publication:
US 2018/0198682
Extracting Features from a Noc for Machine Learning Construction
Infrastructure to Apply Machine Learning for NoC Construction
Application:
15/404,010 →
Publication:
US 2018/0198687
Metrics to Train Machine Learning Predictor for NoC Construction
Application:
15/404,159 →
Publication:
US 2018/0197110
Systems and Methods for NoC Construction
Automatic Buffer Sizing for Optimal Network-on-Chip Design
Automatic Buffer Sizing for Optimal Network-on-Chip Design
STREAMING BRIDGE DESIGN WITH HOST INTERFACES AND NETWORK ON CHIP (NoC) LAYERS
Qos in a System with End-to-End Flow Control and Qos Aware Buffer Allocation
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Interface Virtualization and Fast Path for Network on Chip
Application:
15/829,749 →
Publication:
US 2018/0159786
Traffic Mapping of a Network on Chip Through Machine Learning
Application:
15/854,508 →
Publication:
US 2018/0183726
Cost Management Against Requirements for the Generation of a Noc
Automatic Generation of Power Management Sequence in a Soc or Noc
Application:
15/903,298 →
Publication:
US 2018/0181173
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Interface Virtualization and Fast Path for Network on Chip
Application:
15/903,425 →
Publication:
US 2018/0183721
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Traffic Mapping of a Network on Chip Through Machine Learning
Application:
15/903,502 →
Publication:
US 2018/0183727
Interface Virtualization and Fast Path for Network on Chip
System and Method for Grouping of Network on Chip (Noc) Elements
Application:
15/903,572 →
Publication:
US 2018/0183672
Interface Virtualization and Fast Path for Network on Chip
Automatic Generation of Power Management Sequence in a Soc or Noc
Cost Management Against Requirements for the Generation of a NoC
Traffic Mapping of a Network on Chip Through Machine Learning
Application:
15/903,948 →
Publication:
US 2018/0183728
Cost Management Against Requirements for the Generation of a NoC
Automatic Crossbar Generation and Router Connections for Network-on-Chip (Noc) Topology Generation
System-On-Chip (Soc) Optimization Through Transformation and Generation of a Network-on-Chip (Noc) Topology
Generation of Network-on-Chip Layout Based on User Specified Topological Constraints
Buffer Sizing of a Noc Through Machine Learning
Repository of Integration Description of Hardware Intellectual Property for Noc Construction and Soc Integration
System on Chip (Soc) Builder
Backbone Network-on-Chip (Noc) for Field-Programmable Gate Array (Fpga)
Application:
16/258,205 →
Publication:
US 2019/0266088
Application Mapping on Hardened Network-on-Chip (Noc) of Field-Programmable Gate Array (Fpga)
Enhanced Page Locality in Network-on-Chip (Noc) Architectures
Bandwidth Weighting Mechanism Based Network-on-Chip (Noc) Configuration
Systems and Methods for Maintaining Network-on-Chip (Noc) Safety and Reliability
Application:
16/265,948 →
Publication:
US 2019/0260504
Application Mapping on Hardened Network-on-Chip (Noc) of Field-Programmable Gate Array (Fpga)
Systems and Methods for Facilitating Low Power on a Network-On-Chip
Application:
62/393,465 →
Interface Virtualization and Fast Path for Network on Chip
Application:
62/429,695 →
Traffic Mapping of a Network on Chip Through Machine Learning
Application:
62/439,440 →
Cost Management Against Requirements for the Generation of a NoC
Application:
62/453,431 →
System-On-Chip (Soc) Optimization Through Transformation and Generation of a Network-on-Chip (Noc) Topology
Application:
62/634,015 →
Systems and Methods for Maintaining Network-on-Chip (Noc) Safety and Reliability
Application:
62/634,076 →
Bandwidth Weighting Mechanism Based Network-on-Chip (Noc) Configuration
Application:
62/634,079 →
Automatic Crossbar Generation and Router Connections for Network-on-Chip (Noc) Topology Generation
Application:
62/634,099 →
Enhanced Page Locality in Network-on-Chip (Noc) Architectures
Application:
62/634,100 →
Repository of Integration Description of Hardware Intellectual Property for Noc Construction and Soc Integration
Application:
62/634,111 →
Backbone Network-on-Chip (Noc) for Field-Programmable Gate Array (Fpga)
Application:
62/634,472 →
Application Mapping on Hardened Network-on-Chip (Noc) of Field- Programmable Gate Array (Fpga)
Application:
62/634,587 →
System on Chip (Soc) Builder
Application:
62/634,653 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 15, 2013
From: KUMAR, SAILESH; NORIGE, ERIC; PHILIP, JOJI; ROWLANDS, JOSEPH
To: NETSPEED SYSTEMS
Reel/Frame 030799/0753 →
Assignment of Assignor's Interest
Jul 25, 2013
From: KUMAR, SAILESH; PATANKAR, AMIT; NORIGE, ERIC
To: NETSPEED SYSTEMS
Reel/Frame 030879/0352 →
Assignment of Assignor's Interest
Aug 5, 2013
From: KUMAR, SAILESH; PATANKAR, AMIT; NORIGE, ERIC
To: NETSPEED SYSTEMS
Reel/Frame 030944/0757 →
Assignment of Assignor's Interest
Aug 7, 2013
From: KUMAR, SAILESH; NORIGE, ERIC; ROWLANDS, JOE; PHILIP, JOJI
To: NETSPEED SYSTEMS
Reel/Frame 030965/0017 →
Assignment of Assignor's Interest
Apr 2, 2026
From: INTEL CORPORATION
To: TENSTORRENT USA, INC.
Reel/Frame 074264/0335 →